Real Intent, Inc.

Synopsys, Inc.

Rajeev Kumar Ranjan

Christopher F Morrison

Prakash Narain

John Mark Beardslee

Rajiv Kumar

James Herbert Kukula

Thomas Robert Shiple

Jay Andrew Littlefield

In a finite state machine (FSM) a set of goal states, to be searched for their reachability from a start state, is defined. An overapproximated path is found from a start state to a goal state by a forward approximation technique. The overapproximated path representation relies upon a partitioning of the state and input bits of FSM. A state matrix of the overapproximated path is organized by time-steps of FSMalong a first dimension and by partitions of FSMstate bits along a second dimension. An underapproximated path, along the path of the stepping stone matrix, is determined. Underapproximation is typically accomplished by simulation. A sequence of states to be output is updated with the underapproximated path. If a start to goal state sequence has been found, the procedure ends. Otherwise, the above steps of over and under approximation are repeated, using the results of the last underapproximation as a start state.

Method and apparatus for formally constraining random simulation

A method and apparatus are described that facilitate validation of a hardware design having multiple hierarchical levels. In one embodiment, a representation of the hardware design is received, and the hardware design is validated by performing validation processing on a plurality of sub-problems. Each of the plurality of sub-problems covers a computationally feasible size of the hardware design at a corresponding hierarchical level. In another embodiment, validation of a hardware design includes making use of validation processing previously performed with respect to one or more modules included in the hardware design based on the hierarchical relationship between these modules and other modules included in the hardware design.

Hierarchical functional verification

A method and apparatus for characterizing information about design attributes is described. The characterization process may begin with determining the dependency among the attributes within a hardware design. Once the dependency is determined, the most relevant information about the hardware design attribute may be highlighted. A user can then focus their attention on the highlighted aspects of the design attribute to draw conclusions about the hardware design as a whole.

Method and apparatus for characterizing information about design attributes

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, hardware design defects can be detected using a novel Intent-Driven Verification process. First, a representation of a hardware design and information regarding the intended flow of logical signals among variables in the representation are received. Then, the existence of potential errors in the hardware design may be inferred based upon the information regarding the intended flow of logical signals by (1) translating the information regarding the intended flow of logical signals into a comprehensive set of checks that must hold true in order for the hardware design to operate in accordance with the intended flow of logical signals, and (2) determining if any of the checks can be violated during operation of circuitry represented by the hardware design.

Intent-driven functional verification of digital designs

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, multiple design verification checks associated with a hardware design are linked by determining dependency reationships among the multiple design verification checks. Each of the design verification checks represent a condition that must hold true in order for the hardware design to operate in accordance with an intended flow of logical signals in the hardware design.

Determining dependency relationships among design verification checks

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a comprehensive set of design verification checks may be formulated by applying predetermined properties to an annotated hardware design representation. Information regarding the intended flow of logical signals in the hardware design is received by way of annotations in a control file or annotations embedded in the hardware design representation itself. The annotations include (1) an indication of one or more variables in the representation of the hardware design through which the logical signals pass, and (2) an indication of one or more conditions under which each of the one or more variables are to be associated with each of a set of states. Checks are then automatically formulated based upon a predetermined set of properties that must hold true in order for the hardware design to operate in accordance with the intended flow. Each of the checks is capable of evaluation with reference to the states associated with the one or more variables during propagation of the logical signals.

Automatic formulation of design verification checks based upon a language representation of a hardware design to verify the intended behavior of the hardware design

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Santa Clara, CA, United States of America

Rajeev Kumar Ranjan