Jasper Design Automation, Inc.

Cadence Design Systems, Inc.

Rajeev Kumar Ranjan

Chung-Wah Norris Ip

Kathryn Drews Kranen

Beth C Isaksen

Ziyad Hanna

Habeeb Farah

Craig Franklin Deaton

Georgia Penido Safe

Yann Alain Antonioli

Ross M Weber

Lawrence Loh

Claudionor José Nunes Coelho

Harry David Foster

Antonio Celso Caldeira, Jr

Marcus Vinicius Da Mata Gomes

Per Anders M Franzen

Per Anders M Franzén

Karl Stefan Esbjörner

An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Isolating differences between revisions of a circuit design

An improved approach is provided to implement performance checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis, where the two designs are checked to see if they are equivalent on the transaction-level. Thereafter, the outputs for the transactions are analyzed relative to delay time periods, which allows verification and identification of possible performance issues and differences between the two designs.

Method and system to perform performance checks

A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.

Formal verification coverage metrics for circuit design properties

A computer-implemented method and non-transitory computer readable medium for circuit design verification. A property defined for a circuit design is received, the property having a cone of influence in the circuit design corresponding to a portion of the circuit design capable of affecting the property. Bounded reachability analysis is performed for the circuit design against a set of cover items. The set of cover items are classified into classified cover items based on results of the reachability analysis. Coverage information is generated indicating an amount of formal verification coverage provided by the property. The coverage information is generated based on a first set of the classified cover items that correspond to the cone of influence of the property and that are reached within a particular bound during the reachability analysis.

Formal verification coverage metrics of covered events for circuit design properties

Indexing behaviors and recipes of a circuit design

Comprehending waveforms of a circuit design

Comprehending a circuit design

Generalizing and inferring behaviors of a circuit design

Growing community of inventors

Sunnyvale, CA, United States of America

Rajeev Kumar Ranjan