Intel Corporation

Rajeev K Prasad

Jasmin Ajanovic

Nilesh V Shah

Brian K Langendorf

George R Hayek

James S Coke

Dahmane Dahmani

A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.

Architecture and method for providing guaranteed access for a retrying

A method for converting signals from one arbitration and management protocol to another. The conversion is performed by at least three state machines. The conversion circuit converts a set of signals on the first bus to a bus request signal on the second bus. The conversion circuit also converts a signal from the second bus and a set of signals on the first bus to bus grant and memory acknowledge signals on the first bus.

Method and apparatus for converting a five wire arbitration/buffer

A bridge circuit adapted to be associated with first and second bus circuits which bridge circuit includes a first path including a plurality of buffers for storing data or addresses being transferred from the second bus to the first bus, a circuit arrangement for detecting that an interrupt of a presenting-running operation has occurred, a circuit arrangement for determining the state of the plurality of buffers when an interrupt occurs, and apparatus for flushing only those buffers of the plurality which were storing data for transfer when the interrupt occurred.

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Folsom, CA, United States of America

Rajeev K Prasad