Nvidia Corporation

Advanced Micro Devices Corporation

Rajeev Jayavant

Walter E Donovan

David Wyatt

Thomas Edward Dewey

Ryan Kelsey Albright

David William Nuechterlein

Susheela N Narasimhan

Devarshi Patel

Chris Fox

Mark White

Kelly McArthur

Ben Watkins

Apparatuses, systems, and methods to move end connectors. In at least one embodiment, a linkage system to move an end connector between at least a first position and a second position is driven by an actuator in a first direction to drive movement of the end connector in a second direction, perpendicular to the first direction.

Connector positioning system and method

A technique is disclosed for a graphics processing unit (GPU) to enter and exit a power saving deep sleep mode. The technique involves preserving processing state within local memory by configuring the local memory to operate in a self-refresh mode while the GPU is powered off for deep sleep. An interface circuit coupled to the local memory is configured to prevent spurious GPU signals from disrupting proper self-refresh of the local memory. Spurious GPU signals may result from GPU power down and GPU power up events associated with the GPU entering and exiting the deep sleep mode.

System and method for entering and exiting sleep mode in a graphics subsystem

An apparatus and method for using non-power of two texture maps is described. Normalized texture map coordinates such as s and t are converted from a floating point format to a fixed point format and wrapping operations are performed to produce unnormalized texture map coordinates such as u and v corresponding to non-power of two texture maps.

Method and apparatus for sampling non-power of two dimension texture maps

The present invention introduces circuitry and systems for performing two-dimensional motion compensation using a three-dimensional pipeline, as well as methods of operating the same. According to an exemplary embodiment, image processing circuitry is provided and includes both a two-dimensional image pipeline, which is operable to process two dimensional image data to generate successive two-dimensional image frames, and a three-dimensional image pipeline, which is operable to process three-dimensional image data to render successive three-dimensional image frames. The image processing circuitry further includes dual mode sub-processing circuitry, which is associated with each of the two- and three-dimensional image pipelines. The dual mode sub-processing circuitry is operable to perform motion compensation operations associated with the two-dimensional image pipeline in one mode and to perform rasterization operations associated the three-dimensional image pipeline in another mode.

Circuitry and systems for performing two-dimensional motion compensation using a three-dimensional pipeline and methods of operating the same

An N-way set associative virtual victim cache in which cache accesses are automatically directed only to the data array in the most recently used way. The cache memory comprises: 1) N ways, each of the N ways comprising a data array capable of storing L cache lines and a tag array capable of storing L address tags, each of the L address tags associated with one of the L cache lines; and 2) address decoding circuitry capable of receiving an incoming memory address and accessing a target cache line corresponding to the incoming memory address only in a most recently used one of the N ways.

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Fort Collins, CO, United States of America

Rajeev Jayavant