Xilinx, Inc.

Rajeev Jayaraman

Sudip K Nag

Jason H Anderson

Jason Helge Anderson

Anirban Rahut

Vinay Verma

James L Saunders

Madabhushi V R Chari

Arne S Barras

Sandor S Kalman

Gi-Joon Nam

Jennifer Zhuang

Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed () with at least one design tool. Statistical data is captured () for the at least one design tool and operational attributes thereof are automatically adjusted () in response to the statistical data. A second version of the circuit design is processed () with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed () with at least one design tool in a first iteration. Statistical data is captured () for the at least one design tool and operational attributes thereof are automatically adjusted () for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed () with the at least one design tool having the adjusted operational attributes in the second iteration.

Method and apparatus for implementing a circuit design for an integrated circuit

Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Method and apparatus for facilitating signal routing within a programmable logic device

Methods of estimating routing delays between two points in a programmable logic device (PLD). The invention takes advantage of the fact that there are a finite number of possible routes (routing paths) between any two points in a PLD. In PLDs with a regular and tiled structure, such as field programmable gate arrays, the number of routes between any two points that are likely to be used by the router is relatively small. Thus, given the locations of the two points to be connected, the route most likely to be used by the router can be determined, and an associated delay can be calculated. This associated delay is then reported as the estimated routing delay. This method of delay estimation can be much more accurate than using an average delay. When the delays between possible paths vary widely, the actual delay of a connection can vary widely from the average.

Methods of estimating routing delays during the placement process in programmable logic devices

A method and apparatus for determining routing feasibility of a plurality of nets. Each net has an associated set of one or more routing solutions, wherein each solution specifies one or more routing resources consumed by the net. A liveness Boolean function is generated having variables that represent respective net/solution pairs. If there exists a set of values for the variables such that at least one of the variables for each net is logically true, then the liveness function is true. An exclusivity function is generated using the variables that represent the net/solution pairs. If there exists at least one set of values for the variables such that no resource is used is by more than a predetermined number of nets, then the exclusivity function is true. The nets are routable using the provided solutions if there is one set of values for the variables such that both the liveness and exclusivity functions are true.

Method and apparatus for testing routability

A method and apparatus for placement into a programmable gate array of I/O design objects having different I/O attributes. The I/O attributes of an I/O design object define the electrical characteristics of the design object. The programmable gate array has a plurality of sites (IOBs) arranged into banks supporting a variety of electrical interface characteristics. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between I/O attributes of I/O design objects as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, sets of I/O attributes are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.

Method and apparatus for placement of input-output design objects into a programmable gate array

A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of different input and output voltage standards. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between design object voltage standards as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, standards are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.

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Saratoga, CA, United States of America

Rajeev Jayaraman