Intel Corporation

Tahoe Research, Ltd.

Rajeev D Muralidhar

Harinarayanan Seshadri

Vishwesh M Rudramuni

Youvedeep Singh

Richard Quinzio

Christophe Fiat

Aymen Zayet

Illyas M Mansoor

Rajesh Poornachandran

Barnes Cooper

Bruce L Fleming

Noor Mubeen

Sujith Thomas

Nithish Mahalingam

Rushikesh S Kadam

Tsung-Yuan Charles Tai

Ren Wang

Jr-Shian Tsai

Mesut A Ergin

Suketu R Partiwala

Nivedha Krishnakumar

Christian Maciocco

Alexander W Min

Hsin-Yuo Liu

Manasi Deval

Prakash N Iyer

Rajaram Regupathy

Ajaya V Durg

Ramanathan Sethuraman

Vijayakumar Ashok Dibbad

Satish Prathaban

Ravish Kumar

Ranjeeta Singh

Nirmala Bailur

Arojit Roychowdhury

Srividya Karumuri

Pugi Tang

Rohit Idgunji

Chris Lord

Brinda Kh

Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Power governance of processing unit

Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Platform power consumption reduction via power state switching

A method and device that implements communication over an interconnect to support improved power distribution over the interconnect. The device includes a controller to implement a device policy manager (DPM) to manage power allotment over the interconnect, and a battery feedback mechanism coupled to the controller, the battery feedback mechanism to detect a low or dead battery condition of a connected device over the interconnect and to indicate to the DPM to advertise a higher power charging level to the connected device.

Method, apparatus and system to enhance a device policy manager to manage devices based on battery condition

Methods and apparatus relating to Priority Based Application Event Control (PAEC) to reduce application events are described. In one embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may cause a processor or platform to exit a low power consumption state. In an embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may resume operations after a processor or platform exit a low power consumption state. Other embodiments are also claimed and disclosed.

Priority based application event control (PAEC) to reduce power consumption

Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

Hardware apparatuses and methods to perform transactional power management

Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.

Systems, methods and devices for dynamic power management of devices using game theory

Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., Six) instead of a second low power consumption state (e.g., S) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.

Voltage regulator efficiency-aware system energy management

Technologies for execution trace with automatic event triggering include a computing device that includes an execution trace hub. The trace hub observes execution trace packets and determines whether the execution trace packets match one or more event trigger rules. If an execution packet matches an event trigger rule, the trace hub invokes an event callback. The event callback may be a predefined hardware function of the computing device or a software function. The trace hub may be configured with event trigger rules and associated event callbacks, for example by writing to one or more corresponding configuration space registers. In response to invoking the event callback, the computing device may, for example, output state information of the computing device to a data storage device, halt execution, activate a debug mode of the processor, or execute a software recovery function. Other embodiments are described and claimed.

Trace hub logic with automatic event triggering

The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.

Media hub device and cache

Methods and apparatus relating to Based Priority Application Event Control (PAEC) to reduce application events are described. In one embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may cause a processor or platform to exit a low power consumption state. In an embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may resume operations after a processor or platform exit a low power consumption state. Other embodiments are also claimed and disclosed.

Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination.

Dynamically entering low power states during active workloads

Growing community of inventors

Bengaluru, India

Rajeev D Muralidhar