Hewlett Packard Enterprise Development LP

University of Rochester

Other

University of Utah Research Foundation

Rajeev Balasubramonian

Naveen Muralimanohar

Sandhya Dwarkadas

David H Albonesi

Norman Paul Jouppi

Alan Lynn Davis

Aniruddha Nagendran Udipi

Gregg Bernard Lesartre

Paolo Faraboschi

Alper Buyuktosunoglu

Grigorios Magklis

Niladrish Chatterjee

Greg P Semeraro

Michael L Scott

Jishen Zhao

Alper Buyuktosnoglu

Robert S Schreiber

John B Carter

Liqun Cheng

Karthik Ramani

Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.

Retrieve data block from determined devices

A method to access a memory chip having memory banks includes processing read requests in a read queue, and when a write queue is filled beyond a high watermark, stopping the processing of the read requests in the read queue and draining the write queue until the write queue is under a low watermark. Draining the write queue include issuing write requests in an order based on information in the read queue. When the write queue is under the low watermark, the method includes stopping the draining of the write queue and again processing the read requests in the read queue.

Draining a write queue based on information from a read queue

Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.

Data write to subset of memory devices

Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.

Memory device write based on mapping

A disclosed example apparatus includes a row address register () to store a row address corresponding to a row () in a memory array (). The example apparatus also includes a row decoder () coupled to the row address register to assert a signal on a wordline () of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder () to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

Memory access methods and apparatus

An example system in accordance with an aspect of the present disclosure is to use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED is to be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC information, in response to identifying the error.

Local error detection and global error correction

The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

Memory interface

An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.

Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration

A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.

Dynamic reconfigurable memory hierarchy

Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.

Multiple clock domain microprocessor

Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals

A method for utilizing heterogeneous interconnects comprising wires of varying latency, bandwidth and energy characteristics to improve performance and reduce energy consumption by dynamically routing traffic in a processor environment.

Growing community of inventors

Sandy, UT, United States of America

Rajeev Balasubramonian