Amazon Technologies, Inc.

Cadence Design Systems, Inc.

Rajdeep Mukherjee

Omer Tripp

Ziyad Hanna

Habeeb Farah

Benjamin Meng-Ching Chen

Pranav Garg

Sengamedu Hanumantha Rao Srinivasan

Michael Wilson

Ravi Prakash

Hoan Nguyen

Yingjun Lyu

Neela Sawant

Benjamin Robert Liblit

Code changes may be hierarchically clustered to discover coding practices. Code change graphs for changes to code in a source code repository may be clustered according to hierarchy of different features determined for the source code into groups. The code change graphs in the groups may then be indexed according their similarity with other code change graphs in the groups. Then one or more coding practices corresponding to the indexed code changes may be provided.

Hierarchical clustering for coding practice discovery

An aggregate representation of a collection of source code examples is constructed. The collection includes positive examples that conform to a coding practice and negative examples do not conform to the coding practice. The aggregate representation includes nodes corresponding to source code elements, and edges representing relationships between code elements. Using an iterative analysis of the aggregate representation, a rule to automatically detect non-conformance is generated. The rule is used to provide an indication that a set of source code is non-conformant.

Example-based synthesis of rules for detecting violations of software coding practices

Techniques for program verification are described. An exemplary method includes receiving a request to evaluate code based on a customized rule, the customized rule comprising one or more conditions for which the customized rule is applicable and one or more postconditions to indicate at least one check to perform for a given node in a graph for the code, wherein an application of the customized rule performs one or more of: an interleave between a backward analysis and forward analysis based on user-specified conditions, an analysis between sub-graphs by a query from a first sub-graph to a second sub-graph, and an operation on a sub-graph, storage of a result of the operation on the sub-graph, and usage of the stored result in a subsequent operation; generating a graph for the code; and evaluating the code by applying the customized rule to the generated graph.

Data flow tracking in program verification

The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a reference model including a software specification and an implementation model at a register transfer level. Embodiments may also include generating one or more invariants based upon, at least in part, the reference model, wherein generating one or more invariants includes applying a semantic analysis. Embodiments may further include automatically generating at least one case splitting candidate based upon, at least in part, the one or more generated invariants.

System, method, and computer program product for automatically inferring case-split hints in equivalence checking of an electronic design

The present disclosure relates to a computer-implemented method for use in a formal verification of an electronic design. Embodiments may include receiving a reference model including a software specification, an implementation model at a register transfer level, and a property that analyzes equivalence between the reference model and the implementation model. The method may further include generating one or more case split hints based upon the reference model, that may be used to decompose the design state space into smaller partitions and performing an abstraction operation on a portion of design logic associated with one or more partitions in order to eliminate design elements that are irrelevant to a particular property. Embodiments may also include performing model checking on the abstract models to determine their accuracy.

System, method, and computer program product for sequential equivalence checking in formal verification

The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in part, the specification model. Embodiments may also include applying a machine generated semantic preserving program transformation to the intermediate representation to create a semantically transformed specification model and synthesizing the semantically transformed specification model to generate a formal verification model.

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San Jose, CA, United States of America

Rajdeep Mukherjee