Intel Corporation

Rajay R Pai

Nasser A Kurd

David J O'Brien

R Tim Frodsham

Mike J Tripp

Sarah E Bates

Anne Meixner

Jeff Wight

In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circuit is operating in a loopback test mode. According to a further embodiment, the integrated circuit includes one or more programmable delay circuits coupled to the I/O buffers that permit switching state (AC) loopback timing tests to be conducted.

Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements

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Beaverton, OR, United States of America

Rajay R Pai