Texas Instruments Corporation

Rajavelu Thinakaran

Nitin Kumar Agarwal

Aniruddha Roy

Sumit Dubey

Vineet Mishra

Sumantra Seth

Gautam Salil Nandi

Tanmay Neema

Ashwin Ramachandran

Mahadevan Shankara Venkiteswaran

Kanak Chandra Das

The techniques and circuits, described herein, include solutions for error compensation in source measurement units (SMUs). An example SMU is capable of both sourcing current to a device under test (DUT) and measuring current through the DUT. An SMU may include a sensing resistor coupled in series with the DUT. A voltage across the sensing resistor may be measured by a current sensing amplifier in order to determine the output current through the DUT. In practice, the resistance of the sensing resistor may vary depending on manufacturing tolerances, etc. A gain of the current sensing amplifier may be calibrated in order to compensate for sensing resistor variance, which increases the accuracy with which current to the DUT can be sourced and measured.

Force/measure current gain trimming

Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Precision oscillators that use imprecise components

A system includes a multiplying digital-to-analog converter (MDAC). The system also includes an input-side component coupled to the MDAC and configured to provide a code to the MDAC. The system also includes a reference voltage source coupled to the MDAC and configured to provide a reference voltage to the MDAC. The MDAC comprises a nonlinear calibration circuit configured to adjust an output of the MDAC nonlinearly based on the code, the reference voltage, and an output of the nonlinear calibration circuit.

Multiplying digital-to-analog converter (MDAC) with nonlinear calibration

A multiplying digital to analog converter (MDAC) includes a first resistor configured to be selectively connected to a current output node based on a first bit of a first portion of an input digital code and a second resistor configured to be selectively connected to the current output node based on a second bit of the first portion of the input digital code. A resistance of the second resistor is a resistance of the first resistor scaled by a factor. The MDAC further includes a first capacitor configured to be selectively connected to the current output node based on the first bit of the first portion and a second capacitor configured to be selectively connected to the current output node based on the second bit of the first portion. A capacitance of the second capacitor is a capacitance of the first capacitor scaled by an inverse of the factor.

Multiplying digital to analog converter with increased multiplying bandwidth

At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Attenuating common mode noise current in current mirror circuits

Disclosed examples include switched capacitor integrator circuits including an amplifier, a feedback capacitor, a sampling capacitor, a loading capacitor and a switching circuit, along with a controller that operates the switching circuit to sample an input signal to the sampling capacitor during a sample portion of a given sample and hold cycle, to couple the sampling capacitor to an amplifier input during a first hold portion of each sample and hold cycle, and to couple the sampling capacitor and the loading capacitor to the amplifier input in a second hold portion of each sample and hold cycle to reduce the bandwidth and power consumption by the integrator circuit.

Low power switched capacitor integrator, analog-to-digital converter and switched capacitor amplifier

A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a frequency-to-voltage (F2V) converter. The F2V converter, for example, includes a frequency target control input for selecting an operational frequency and in response generates a frequency control signal using a DAC (digital-to-analog converter). The example F2V converter is arranged using a split capacitor DAC to provide a linear voltage response over a range of trim codes. The clock generator is arranged to generate the converter clock signal in response to the frequency control signal.

Tunable frequency-to-voltage controlled oscillation

A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored CMOS latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase.

Low-power offset-stored latch

A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a 'T' configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Switch architecture at low supply voltages

A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.

Voltage-mode driver with pre-emphasis

A dynamic biasing circuit includes a first input pair coupled to a second input pair, the first input pair including a first transistor and a second transistor with sources coupled to each other, and the second input pair comprising a third transistor and a fourth transistor with sources coupled to each other, the sources receiving a bias current. A first current mirror that generates an output current is coupled to the first input pair. A second current mirror is coupled to the first input pair and the second input pair. The second current mirror is configured to force the current to drop in the fourth transistor in response to sensing a current drop in the first transistor such that the bias current flows through the second and third transistors that boosts the output current.

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Bengaluru, India

Rajavelu Thinakaran