Advanced Micro Devices Corporation

Rajat Roy

Jeffrey Roy Dwork

Jerry Weiming Kuo

Alok Singh

Robert Alan Williams

Ching Yu

Jenny Liu Fischer

Andy P Annadurai

A network interface for a workstation, configured to be powered down to a standby mode while the network interface remains in a powered-up condition, includes a bypass circuit configured to enable configuration registers in the network interface to complete loading of configuration information in a known state, regardless of an absence of an external data clock from the network during the initialization interval. The bypass circuit ensures that the configuration registers in the network interface that require a network clock (e.g., a transmit clock or a receive clock) are maintained in a known state to enable the network interface to be independently initialized. One example of the bypass circuit holds a power on reset signal until the necessary network clock signal is detected for a predetermined number of detected clock cycles. Another example of the bypass circuit substitutes the absent clock signal with an independent clock source in response to the power on reset signal and holds the power on reset signal for a predetermined number of independent clock cycles, followed by switching back to the signal path providing the required clock signal. The disclosed arrangement enables the network interface device to initialize upon power up and start to monitor network media for wakeup traffic indicating the host computer in the workstation should be activated.

Apparatus and method for selectively controlling clocking and resetting

A data structure to provide high performance in the transmit portion of an ethernet controller. The data structure includes the data to be transmitted, the STATUS information of the data to be transmitted, and the DESCRIPTOR information of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32 bit STATUS information is organized in four 8-bit bytes in a 32 bit row, and the 32 bit DESCRIPTOR information is organized in four 8-bit bytes in a 32 bit row. A one-bit tag field is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.

Data structure to support multiple transmit packets for high performance

An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending requests from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

Address generation and data path arbitration to and from SRAM to

A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.

Method of identifying end of pocket by writing the address of last data

A circuit and method for switching between different frequency clock domains that are out of phase. The circuit has a select input for selecting which frequency domain is to be output, a first circuit associated with the first clock domain, and a second circuit associated with the second clock domain. The first and second circuits are responsive to the select input and work together to disengage the first clock before the second clock is engaged.

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Sunnyvale, CA, United States of America

Rajat Roy