International Business Machines Corporation

Rajat Rao

Patrick James Meaney

Ashutosh Mishra

Christian Jacobi

Alper Buyuktosunoglu

Bulent Abali

Robert J Sonnelitter, Iii

Glenn David Gilda

Arthur J O'Neill

Arun Joseph

Hubert Harrer

Raj Kumar Gajavelly

Jason Andrew Thompson

Xiaomin Duan

Abinaya B

Michael Jason Cade

Nandini Gaadam Nagaraj

Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: performing order preserving compression of a multiple column index table of a database to provide an encoded index table sorted by an initial column, wherein the multiple column index table includes the initial column and one or more subsequent column; and determining, in dependence on a result of the performing the order preserving compression, at least one modification factor for respective ones of the one or more subsequent column.

Multiple column order preserving compression

A method for encrypting frames transmitted from a transmitter to a receiver includes transmitting unencrypted training frames of a set from the transmitter to the receiver, with each training frame scrambled prior to transmission on an output of a counter of the transmitter and a training frame, where each scrambled training frame is unencrypted. A control signal from the transmitter is transmitted from the transmitter to the receiver after the training frames. After transmitting the control signal to the receiver, a frame modified to include error detection information is encrypted using an encrypted counter block that is generated from the output of the counter. The encrypted modified frame is transmitted from the transmitter to the receiver.

Encrypting data exchanged between components in a link layer with automatic locking between the transmitting component and the receiving component

A multiplexer logic device is automatically identified in a hardware definition language of a design. One or more verification properties of the multiplexer logic device are generated to be used in validation of a selected processing condition of the multiplexer logic device. The one or more verification properties and one or more constraints obtained from software and hardware information relating to the multiplexer logic device are provided as input to a formal verification technique. Verification is performed using the formal verification technique to validate the selected processing condition. Based on the performing verification indicating a failure to comply with the selected processing condition, debugging of the multiplexer logic device is performed.

Co-debug of processing conditions of logic devices

A computer system, computer readable storage medium, and computer-implemented method for dynamically degrading a link between multiple processing devices to facilitate uninterrupted service between the multiple processing devices. The method includes determining a number of undegraded lanes within the link. The method also includes determining, subject to the number of undegraded lanes, a first operational degrade mode for the link. The method further includes initiating a retrain of the link to a second operational degrade mode. The method also includes dynamically, subject to the first degrade mode of operation, determining one or more message packet types to transmit through the link during the link retrain, thereby facilitating uninterrupted service between the multiple processing devices.

Dynamic multi-lane degrade capability to facilitate uninterrupted service

A computer-implemented method includes receiving performing a fused modular multiply and add operation to compute d=((a*b)+c) % p, wherein a, b, and c, are provided as a set of operands. A first multiply-and-accumulate unit computes a binary multiplication to compute a*b. A second multiply-and-accumulate unit computes a first intermediate result by updating a result of the binary multiplication using p. An accumulator of a third multiply-and-accumulate unit is initialized with c. The third multiply-and-accumulate unit computes a second intermediate result using the first intermediate result and c. An adder unit subtracts a portion of the second intermediate result from a portion of the result of the binary multiplication. The output of the adder is provided as a result of the fused modular multiply and add operation.

Fused modular multiply and add operation

Embodiments are directed to elliptic curve cryptography scalar multiplications in a generic field with heavy pipelining between field operations. A bit width is determined of operands in data to be processed by a modular hardware block. It is checked whether the bit width of the operands matches a fixed bit width of the modular hardware block. In response to there being a match, the modular hardware block processes the operands. In response to there being a mismatch, the operands are modified to be accommodated by the fixed bit width of the modular hardware block.

Pipelined hardware to accelerate modular arithmetic operations

Aspects of the invention include physical design-optimal Dadda architectures that scale with increasing operand size. Partial product arrays can be generated for two n-bit operands and columns in the partial product arrays can be shifted to a first row. The number of partial products in each column can be iteratively reduced across one or more stages until each column has at most two partial products. At each stage a maximum column height is determined and each column having a height greater than the maximum column height is reduced using half-adders and full-adders. Result bits of the half-adders and the full-adders are placed at the bottom of the current column and carry bits of the half-adders and the full-adders are placed at the bottom of the next column.

Dadda architecture that scales with increasing operand size

Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Cable pair concurrent servicing

Cryptographic-related processing is facilitated by obtaining multiple input operands, and packing the multiple input operands together to form a packed integer. The packed integer is an n-bit integer including multiple slots, where input operands of the multiple input operands are packed into every other slot of the multiple slots, and each slot of the multiple slots has a bitwidth k. Further, the process includes providing the packed integer as input to an n-bit accelerator to facilitate performing one or more predefined operations using the packed integer, to transform the packed integer into result data which facilitates cryptographic-related processing.

Accelerated cryptographic-related processing

Cryptographic-related processing is performed using an n-bit accelerator. The processing includes providing a binary operand to a multiply-and-accumulate unit of the n-bit accelerator. The multiply-and-accumulate unit performs an operation using the binary operand and a predetermined fractional constant F to obtain an operation result, and rounds the operation result by discarding x least-significant bits of the operation result to obtain a fractionally-scaled result, where x is a configurable number of bits to discard from the operation result, and the fractionally-scaled result facilitates performing the cryptographic-related processing.

Accelerated cryptographic-related processing with fractional scaling

Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer.

Fast clear memory of system memory

Embodiments are directed to selecting a multiplication operation to be scheduled in a first stage of an execution schedule, the multiplication operation meeting a first condition of having no dependency. An addition/subtraction operation is selected to be scheduled in the first stage of the execution schedule responsive to meeting the first condition. A process is performed which includes selecting another multiplication operation to be scheduled in a next stage of the execution schedule responsive to meeting the first condition or a second condition, the second condition including having a dependency that is fulfilled by a previous stage. The process includes selecting another addition/subtraction operation to be scheduled in the next stage of the execution schedule responsive to meeting the first or second condition, and repeating the process until each operation has been scheduled in the execution schedule, where the execution schedule is configured for execution by an arithmetic logic unit.

Scheduling atomic field operations in jacobian coordinates used in elliptic curve cryptography scalar multiplications

A method for transcoding an encoded video stream uploaded to a host server that includes a video transcoding engine connected to the server. At least one processor of the video transcoding engine receives an encoded video stream from a client computing device in which the encoded video stream is directly received by the video transcoding engine connected to the host server and the video transcoding engine has direct access to a non-volatile memory of the host server. The at least one processor of the video transcoding engine generates one or more transcoded files in real-time from the encoded video stream. The at least one processor transfers the one or more transcoded video files from the video transcoding engine directly to the non-volatile memory of the host server.

Video stream transcoding with reduced latency and memory transfer

Provided are embodiments for a circuit comprising for performing hardware acceleration for elliptic curve cryptography (ECC). The circuit includes a code array comprising instructions for performing complex modular arithmetic; and a data array storing values corresponding to one or more complex numbers. The modular arithmetic unit includes a first multiplier and a first accumulation unit, a second multiplier and a second accumulation unit, and a third multiplier and a third accumulation unit, wherein the first, second, and third multiplier and accumulation units are cascaded and configured to perform hardware computation of complex modular operations. Also provided are embodiments of a computer program product and a method for performing the hardware acceleration of super-singular isogeny key encryption (SIKE) operations.

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Bengaluru, India

Rajat Rao