Cadence Design Systems, Inc.

Rajat Kanti Mitra

Chandrashekar Lakshminarayanan Chetput

Aaron Mitchell Spratt

Nan Zhang

William Scott Cranston

Joseph Leo Zielke, Jr

The present disclosure relates to a computer-implemented method for mixed signal design verification. Embodiments may include receiving, using a processor, an electronic circuit design and compiling and elaborating the electronic circuit design. Embodiments may also include simulating the electronic circuit design and updating, during the simulating, a System Verilog User-Defined Resolution function ('SV-UDR') associated with the electronic circuit design.

System, method, and computer program product for mixed signal verification

The present disclosure relates to a computer-implemented method for simulating a circuit design having a discrete domain segment connected to a continuous domain segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the discrete domain segment and the continuous domain segment. The method may also include splitting the discrete domain segment into a plurality of transistor network models to provide for bi-directional transfer of data between the continuous domain segment and the discrete domain segment, wherein at least one of the plurality of transistor network models utilizes only one or more drivers external to a module.

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Bedford, MA, United States of America

Rajat Kanti Mitra