Cypress Semiconductor Corporation

Rajat Gupta

K S Anil

Sunil Thamaran

Thomas Mathew

Pradeep Kumar Mishra

Biswa M Deb

An integrated circuit generally comprising a plurality of input pads, an input circuit, and a core circuit. The input pads may be configured to receive a plurality of first input signals. The input circuit may be configured to generate a plurality of second input signals (i) equal to the first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by the first signals while in a test mode. The core circuit may be responsive to the second input signals.

Reducing tester channels for high pinout integrated circuits

An apparatus comprising a first oscillator, a second oscillator and a logic circuit. The first oscillator circuit may be configured to generate a first clock signal. The second oscillator circuit may be configured to generate a second clock signal. The logic circuit may be configured to generate an output clock signal by selecting either the first clock signal or the second clock signal.

Instantaneous start up oscillator

An apparatus comprising a first circuit and a timing circuit. The first circuit may be configured to generate an output clock signal that may compensate for oscillation build-up and stabilization time after a power up. The timer circuit may be configured to provide timing in response to the output clock signal.

Compensation of crystal start up for accurate time measurement

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first signal comprising a series of one or more pulses. The second circuit may be configured to generate a second signal in response to the first signal. The second signal may be configured to control the reset of an external device. In one example, the present invention may be implemented as a power on reset circuit.

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Bengaluru, India

Rajat Gupta