Texas Instruments Corporation

Stmicroelectronics Pvt. Ltd.

Sicronic Remote Kg, LLC

Rajat Chauhan

Vipul Kumar Singhal

Divya Kaur

Vinod J Menezes

Mahesh Madhukar Mehendale

Danielle Griffith

Jayateerth Pandurang Mathad

Sunil Chandra Kasanyal

Rajesh Kaushik

Per Torstein Roine

Kaichien Tsai

Bernhard Ruck

Srikanth Srinivasan

James N Murdock

Joseph Alan Sankman

Siva Srinivas Kothamasu

Prajkta Vyavahare

Rishav Gupta

Manikandan Rr

Ankur Gupta

Keith Edmund Kunz

Vinayak Ashok Ghatawade

Sandeep Shylaja Krishnan

Keerthinarayan P Heragu

Avinash Shreepathi Bhat

Devraj Matharampallil Rajagopal

Adeel Ahmad

Per Torstein Røine

Venkateswara Reddy P

Sundeep Lakshmana Javvaji

Karthik Rajagopal

Vikas Narang

Manoj Kumar Sharma

Rr Manikandan

Yash Didhe

Naman Gupta

Ashutosh Chitnis

Shuvam Prasad

Santhosh Kumar Srinivasan

Likhita Chandrashekara

Chintamani Keshav Bhaktavatson

A float detector includes a latch and a float detection circuit. The latch includes a latch output and an input/output (I/O) terminal. The I/O terminal is coupled to an input terminal. The float detection circuit includes a detection input, a drive output, and a float detection circuit. The detection input is coupled to the latch output. The drive output is coupled to the I/O terminal. The float detector is configured to provide a drive signal at the drive output, and determine that the input terminal is floating based on a latch output signal received at the detection input responsive to the drive signal.

Floating pin detection

One example includes an integrated circuit with a sense amplifier that includes a first inverter having a first positive power terminal, a first input and a first output; and a second inverter having a second positive power terminal, a second input connected to the first output and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power terminal. A fuse is connected between the positive voltage rail and the first positive power terminal.

Ultra-low power, high speed poly fuse eprom

In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. A voltage divider network is coupled to the second stage. The circuit includes an output transistor having first and second terminals, in which the first terminal of the output transistor is coupled to the first stage, and the second terminal of the output transistor is coupled to the voltage divider network.

Low noise high precision voltage reference

In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. An output transistor is coupled to the first stage and to the current mirror circuit. A voltage divider network is coupled to the output transistor, and a power source is coupled to the second stage and to the voltage divider network.

Temperature drift correction in a voltage reference

A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

Trim/test interface for devices with low pin count or analog or no-connect pins

Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.

Accuracy trim architecture for high precision voltage reference

One example relates to a monitoring circuit that includes a capacitive digital-to-analog converter that receives a binary code, a reference voltage, a monitored voltage, and a ground reference, the capacitive digital-to-analog converter outputting an analog signal based on the binary code, the reference voltage, the monitored voltage, and the ground reference. The monitoring circuit further includes a comparator including a first input coupled to receive the analog signal and a second input coupled to the reference voltage, the comparator comparing the analog signal to the reference voltage and outputting a comparator signal based on the comparison. The monitoring circuit yet further includes a binary code generator that generates the binary code based on the comparator signal, the binary code approximating a magnitude of the monitored voltage.

Voltage monitor using a capacitive digital-to-analog converter

A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

Supply voltage regulator

In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (R) of a differential amplifier stage of the circuit; and trimming a first resistor (R) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (R) of the differential amplifier stage, a third resistor (R) of the scaling amplifier stage, and a fourth resistor (R) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.

Two-temperature trimming for a voltage reference with reduced quiescent current

An electronic circuit includes a first transistor, a second transistor, and a variable resistor. The first transistor has a first threshold voltage. The second transistor has a second threshold voltage that is different from the first threshold voltage. The second transistor is coupled to the first transistor. The variable resistor is coupled to the first transistor and the second transistor. The variable resistor is configured to adjust a temperature coefficient of the electronic circuit. The electronic circuit is configured to generate a reference voltage based on a difference of the first threshold voltage and the second threshold voltage.

Voltage threshold gap circuits with temperature trim

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node.

Voltage sensing circuit

An electronic device having multiple power output circuits that individually include a switch control input, a bypass control input, an output transistor and an output control circuit that includes an RC circuit with a resistor and a capacitor coupled to the output transistor gate and a bypass switch in parallel with the RC circuit resistor. The electronic device includes a controller that selects one of the power output circuits for a given power transfer cycle, closes the bypass switch to bypass the resistor of the selected power output circuit and turns the output transistor of the selected power output circuit on to transfer current from the inductor to a load of the selected power output circuit.

Single inductor multiple output regulator

A power-on-reset (POR) circuit includes an NFET branch and a PFET branch. The NFET branch includes: an n-channel field effect transistor (NFET) having a first threshold voltage; and a first quiescent bias current source coupled between a supply terminal and the NFET. The PFET branch includes: a p-channel field effect transistor (PFET) having a second threshold voltage; and a second quiescent bias current source coupled between a ground terminal and the PFET. The POR circuit is configured to provide a POR signal at an output terminal based on: the first threshold voltage or the second threshold voltage, whichever is larger; and a voltage margin. The output terminal is coupled between the PFET branch and the second quiescent bias current source.

Threshold tracking power-on-reset circuit

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Bengaluru, India

Rajat Chauhan