Xilinx, Inc.

Rajat Aggarwal

Srinivasan Dasasathyan

Guenter Stenz

Qiang Wang

Sudip K Nag

Sridhar Krishnamurthy

Jason Helge Anderson

Aaron Ng

Sabyasachi Das

Zhiyong Wang

Ruibing Lu

Victor Slonim

Marvin Tom

Sanjeev Kwatra

James L Saunders

Vishal Suthar

Hasan Arslan

A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

Interactive multi-step physical synthesis

A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.

Implementing sub-circuits with predictable behavior within a circuit design

A method of component placement for a multi-die integrated circuit (IC) can include partitioning a plurality of components of a netlist among a plurality of dies of the multi-die IC and selecting a superimposition model specifying a positioning of at least two of the plurality of dies at least partially superimposed with respect to one another. The method also can include assigning, by a processor, components of the netlist to hardware units within each of the plurality of dies according, at least in part, to a wire-length metric calculated using the superimposition model.

Routability based placement for multi-die integrated circuits

A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.

Method of placing input/output blocks on an integrated circuit device

A computer-implemented method of implementing a circuit design within an integrated circuit (IC) can include, within an undirected graph representing the circuit design comprising nodes and edges, wherein each node represents a complex function block (CFB) or a pre-placed component of the circuit design and each edge represents at least one connection linking a pair of CFBs of the circuit design, determining an edge weight for each edge. The CFBs can be initially placed and a distance between each pair of CFBs joined by an edge of the undirected graph can be calculated. The CFB placement can be annealed by minimizing a cost function that calculates, for each edge, a product of the edge weight and the distance between the pair of CFBs joined by the edge. The cost function also can sum the products for each edge. The CFB placement can be stored.

Placing complex function blocks on a programmable integrated circuit

The availability of device resources of an IC are quantified for a circuit design by building a representation of resource sites for the IC. Initial availability values are assigned to the resource sites, and any components having locking constraints are identified and placed into their respective sites. From the remaining resource sites, candidate sites for a component of the circuit design are identified. The candidate sites are summed, and the initial availability values of the candidate sites are modified according to the sum.

Resource mapping of functional areas on an integrated circuit

A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow prior to a selected task that does not recognize a constraint, wherein the preprocessing task introduces a modification into the circuit design according to the constraint. The circuit design including the modification can be processed through the selected task of the CAD flow. A reversal task can also be inserted into the CAD flow, wherein the reversal task removes the modification introduced into the circuit design by the preprocessing task. The method further can include processing the circuit design through at least one other task of the CAD flow and outputting the processed circuit design.

Processing constraints in computer-aided design for integrated circuits

A method () of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device () and defining modules having components of a same type (). A set of shapes associated with a module can be determined (). The circuit design can be annealed () to determine a floorplan using the cost function and the set of shapes for the module.

Method system and apparatus for floorplanning programmable logic designs

A method of designing a programmable logic device can include receiving a modification to a programmable logic device that has been floorplanned. Modules of the programmable logic device that have been changed by the modification can be identified. The changed modules can be floorplanned thereby determining a placement solution that does not violate boundaries of unchanged modules. The programmable logic device then can be placed and routed.

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Los Altos, CA, United States of America

Rajat Aggarwal