International Business Machines Corporation

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Advanced Micro Devices Corporation

Infineon Technologies North America Corp.

Rajarao Jammy

Vijay Narayanan

Vamsi Krishna Paruchuri

Cyril Cabral, Jr

Eduard Albert Cartier

Jack Allan Mandelman

Martin Michael Frank

Evgeni Petrovich Gousev

Michael Patrick Chudzik

Supratik Guha

Johnathan E Faltermeier

Matthew Warren Copel

Carl John Radens

Nestor A Bojarczuk, Jr

Bruce Bennett Doris

Oleg Gluschenkov

Rama Divakaruni

Joseph Francis Shepard, Jr

Helmut Horst Tews

Veeraraghavan S Basker

Hariklia Deligianni

Katherine Lynn Saenger

Paul Charles Jamison

Ulrike Gruening

Chun-Yung Sung

Clement Hsingjen Wann

Dureseti Chidambarrao

Keith Kwong Hon Wong

Tze-Chiang Chen

Barry P Linder

Jochen C Beintner

Sunfei Fang

Christopher Carr Parks

Kenneth T Settlemyer, Jr

Jeffrey P Gambino

Yun Yu Wang

Ying Di Zhang

Richard Stephan Wise

Sufi Zafar

Meikei Ieong

Yun-Yu Wang

Byeong Yeol Kim

Fenton Read McFeely

Alessandro Cesare Callegari

Hongwen Yan

Huilong Zhu

Ghavam G Shahidi

Sampath Purushothaman

Zhijiong Luo

Christian Lavoie

Laertis Economikos

Brian Joseph Greene

Robert H Dennard

Omer H Dokumaci

Chandrasekhar Narayan

Emanuel Israel Cooper

Anna Wanda Topol

Kwong Hon Wong

Bruce Kenneth Furman

Paul Christian Parries

Stephan Kudelka

Xiaoyan Shao

Christopher Peter D'Emic

Uwe Paul Schroeder

Alessandro Curioni

Michelle Leigh Steen

Michael Abramovich Gribelyuk

Suryanarayan G Hegde

Lawrence Alfred Clevenger

David V Horak

Chung H Lam

Steven J Holmes

Toshiharu Furukawa

Ramachandra Divakaruni

Kevin K Chan

Mark Charles Hakey

Sebastian Theodore Ventrone

Ryota Katsumata

Baozhen Li

Paul Michael Solomon

Lubomyr Taras Romankiw

Bomy A Chen

Bernhard Sell

Gary Bela Bronner

Hussein Ibrahim Hanafi

Fen Chen

Keitaro Imai

James N Pan

David Edward Kotecki

Michael P Belyansky

Viraj Yashawant Sardesai

Matthias Goldbach

William H Ma

Harald Seidl

Nivo Rovedo

Byeongju Park

Thomas Safron Kanarsky

Siddhartha Panda

John A Miller

John G Pellerin

An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.

Method and apparatus for electroplating on SOI and bulk semiconductor wafers

Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

Method and apparatus for electroplating on soi and bulk semiconductor wafers

The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800&#xb0; C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8&#xd7;10charges/cmor less, a peak mobility of about 250 cmV-s or greater and substantially no mobility degradation at about 6.0&#xd7;10inversion charges/cmor greater.

Method of forming metal/high-&#x3ba; gate stacks with high mobility

An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors

The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Stabilized metal gate electrode for complementary metal-oxide-semiconductor ('CMOS') applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy comprises a metal selected from the group consisting of Re, Ru, Pt, Rh, Ni, Al and combinations thereof and an element selected from the group consisting of W, V, Ti, Ta and combinations thereof.

Metal gate electrode stabilization by alloying

A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow

A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiOand a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

Low threshold voltage semiconductor device with dual threshold voltage control means

An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

Formation of fully silicided metal gate using dual self-aligned silicide process

Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.

Introduction of metal impurity to change workfunction of conductive electrodes

A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlON. The high k dielectric can be HfO, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/HOperoxide solution.

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics

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Hopewell Junction, NY, United States of America

Rajarao Jammy