National Semiconductor Corporation

Texas Instruments Corporation

Rajaram Subramoniam

Gerard G Socci

Gianpaolo Lisi

Ali Djabbari

Kosha Mahmodieh

Swaminathan Sankaran

Bradley Allen Kramer

Ali Kiaei

Debarag Banerjee

Jianhui Zhang

Karim Nassiri Toussi

Andrew Ronald Chemistruck

Huoy-Bing Lim

In a first inductive structure, a first data coil includes: a first portion for conducting a first common mode current in a first direction; and a second portion for conducting a second common mode current in a second direction opposite the first direction. The first and second portions of the first data coil are connected at a first node. In a second inductive structure, a second data coil includes: a first portion for conducting a third common mode current in the first direction; and a second portion for conducting a fourth common mode current in the second direction. The first and second portions of the second data coil are connected at a second node galvanically isolated from the first node. The first, second, third and fourth common mode currents are induced by a common mode transient.

Inductive structures with improved common mode transient immunity

An inductive structure includes a power coil and a data coil. The data coil is substantially centered within the power coil. A first portion of the data coil conducts current in a first direction. A second portion of the data coil conducts current in a second direction opposite the first direction. The first portion of the data coil is connected at a node to the second portion of the data coil. The node is coupled to a ground.

Inductive structures with reduced emissions and interference

A solar panel array for use in a solar cell power system is provided. The solar panel array includes a string of solar panels and multiple voltage converters. Each voltage converter is coupled to a corresponding solar panel in the string of solar panels. The solar panel array also includes multiple maximum power point tracking (MPPT) controllers. Each MPPT controller is coupled to a corresponding solar panel in the string of solar panels. Each MPPT controller is configured to sense an instantaneous power unbalance between the corresponding solar panel and an inverter.

System and method for over-voltage protection of a photovoltaic system with distributed maximum power point tracking

A system includes a master device and multiple slave devices. The system also includes multiple bus interfaces forming a communication bus that couples the master and slave devices. Each bus interface includes a primary interface unit configured to communicate over first and second buses, where the first and second buses form a portion of the communication bus. Each bus interface also includes a secondary interface unit configured to communicate with the primary interface unit and to communicate with one of the slave devices over a third bus. Each bus interface further includes an isolator configured to electrically isolate the primary interface unit and the secondary interface unit. The primary interface unit is configured to receive multiple commands over the first bus, execute a first subset of commands, transmit a second subset of commands over the second bus, and transmit a third subset of commands over the third bus.

Isolated communication bus and related protocol

A fast, low-complexity detection scheme for determining the delays and gains of different propagation paths (i.e., multi-paths) of a received WCDMA signal. The method utilizes a continuous pilot channel that is scrambled by an known pseudo-random sequence. The received signal is provided to a multi-path searcher that passes the received signal through a matched filter with a specified number of taps. The matched filter correlates the received signal with the pilot channel. The multi-path gain and delay detection is then performed, and the delays and gains are reported for use in the WCDMA system.

Method and apparatus for multi-path delay spread detection in wideband CDMA systems

A channelization code is generated in response to a spreading factor and a code number. The code number is right justified to provide a right-justified code number. The right-justified code number is stored in an eight-bit register. An eight-bit binary counter is arranged to provide a binary count. The binary counter is reset when the binary count reaches a value equal to the spreading factor minus one. A channelization logic circuit is configured to convert the binary count and the stored right-justified code number into the channelization code. According to one example, the channelization logic circuit comprises eight AND gates and eight XOR gates. A channelization code generator circuit may be integrated into an integrated chip that has a small silicon area and low power consumption.

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Cupertino, CA, United States of America

Rajaram Subramoniam