Intel Corporation

Rajaram Regupathy

Vincent J Zimmer

Sajal Kumar Das

Abdul Rahman Ismail

Subrata Banik

Saranya Gopal

Asad Azam

Peter Ewert

Reuven Rozic

Nirmala Bailur

Gaurav Singh

Purushotam Kumar

Vrukesh V Panse

Abhilash K V

Rajeev D Muralidhar

Julius Yuli Mandelblat

Rolf H Kuehnis

Ziv Kabiry

Dmitriy Berchanskiy

Paul D Crutcher

Jenny Pelner

Khaled Almahallawy

Ravi Poovalur Rangarajan

Kalyan Kondapally

Paul Sathya Chelladurai

Vns Murthy Sristi

Vagdevi P

V Sowmya

Balaji Manoharan

Maulik V Vaghela

Tomer Savariego

Oren Novitzky

Maulik Vaghela

Jenny M Pelner

Stephanie Wallick

Methods, apparatus, systems, and articles of manufacture to increase boot performance are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: during a boot process: identify a boot task that is to be performed during the boot process; execute the boot task using a first processor component; collect data corresponding to the execution of the boot task on the first processor component; categorize the boot task based on the collected data; and generate an entry for a boot table based on the categorization, the boot table used to schedule the boot task on at least one of the first processor component or a second processor component different than the first processor component based on the categorization.

Methods and apparatus to increase boot performance by categorizing boot tasks

Buses such as USB4 or Thunderbolt 4 buses may allow for device combinations that actually cannot be accommodated on the bus. A monitoring component, e.g., software and/or hardware component, such as an Operating System (OS) policy manager, may monitor a bus for events identifying changes to devices on the bus. The monitoring component may influence mode changes to hardware/software, such as to the USB configuration, device driver settings, attached device settings, and/or settings for devices attaching to the bus. Influenced changes facilitate accommodating changes to the devices attached to the bus. For example, if a display is attached and it would exceed available bus bandwidth, cause an excess system load, or cause some other problem, rather than fail to enumerate the display, instead hardware and/or software associated with the bus may be influenced to result in a resolution reduction for the display to accommodate it attaching to the bus.

Dynamically influencing bandwidth

In one embodiment, an apparatus includes interconnect circuitry to implement one or more layers of a Universal Serial Bus (USB)-based protocol. The interconnect circuitry can implement a first USB-based interface and a second USB-based interface. The apparatus further includes telemetry circuitry to generate telemetry data, cause the telemetry data to be transmitted via the first USB-based interface, detect a power state transition in the apparatus, cause the telemetry data to be buffered based on detecting the power state transition, and cause the buffered telemetry data to be transmitted via the second USB-interface based on a set interface request indicating the second USB-interface.

Dynamic functional input/output (IO) device interface selection through power state transitions

Universal Serial Bus (USB) Power Delivery is augmented by allowing devices that attach to the USB to include and/or have access to an enhanced device policy manager (eDPM) so that device information such as status, state, or requirements, such as power requirements, may be at least be shared by the eDPMs between, for example, a host device on the bus, a secondary device providing power to devices on the bus, and a new device attaching to the bus. Sharing device information facilitates the host having contextual awareness for the attaching device and assists with determining whether the attaching device may be enumerated on the bus. If not, such as due to insufficient power available from the secondary device, the host and/or secondary device may seek to influence bus devices to change an operating mode to accommodate the attaching device.

Peer-influenced enhanced USB power delivery

A data scaling module for USB4 that embodies display driver (DD) and connection manager (CM) operations. Periodic and aperiodic transfer requests are monitored. The periodic BW activity on periodic peripherals, such as display panels (DPs) is monitored, and determinations as to reduced periodic activity on a DP are made. Responsive to receiving a high aperiodic bandwidth request, the original refresh rate for the DP is reduced. The newly freed USB4 BW is provided for the aperiodic task. At completion of the aperiodic task, the DD increases the refresh rate to its original value.

Apparatus and methods for universal serial bus 4 (USB4) data bandwidth scaling

A scheme to enhance USB-C port policy by dynamically entering optimal USB-C alternate mode with an informed feedback mechanism to OSPM which influences the USB-C port DPM. In some embodiments, when a USB4 device is connected to a port, the scheme parses the alternate modes and power characteristics from the class descriptor information of the enumerated device. In some embodiments, the parsed information is provided as a feedback to the OSPM that instructs the USB-C/PD DPM to enter or switch mode that shall meet the policy criteria of the OS configuration in a dynamic command control from the OS. In some embodiments, the USB-C DPM dynamically chooses to enter an optimal mode based on the power and thermal conditions information available in the embedded controller and indicate the OS about the changes. As such, the OS is aware of the USB operation mode.

Dynamic USB-C mode selection OSPM policy method and apparatus

In one embodiment, an apparatus includes a host controller to implement one or more layers of a Universal Serial Bus (USB)-based protocol to provide an interconnect for a plurality of devices. The host controller is to monitor control plane messages on the interconnect, detect, in the control plane messages, a power state change command for a device coupled to the interconnect, wherein the devices utilizes a tunneled protocol on the interconnect, and modify power distribution for one or more other devices of the interconnect based on detecting the power state change command.

System power management in multi-port I/O hybrid systems

Systems, apparatuses and methods may provide for technology that identifies, during a first boot process, whether at least one task associated with at least one software program is set to occur in a single-threaded process or a multithreaded process, in response to the at least one task being set to occur in the multithreaded process, executing the at least one task in the multithreaded process during the first boot process, and in response to the at least one task being set to occur in the single-threaded process, executing the at least one task in the single-threaded process during the first boot process.

Firmware boot task distribution to enable low latency boot performance

A data processing system comprises a processing core to execute a basic input/output system (BIOS) as part of a boot process. The data processing system also comprises static random-access memory (SRAM) in communication with the processing core. The data processing system also comprises a pre-BIOS component in communication with the SRAM. The pre-BIOS component is configured to execute a pre-BIOS block before the processing core begins executing the BIOS. The pre-BIOS block, when executed by the pre-BIOS component, causes the pre-BIOS component to (a) initialize the pre-BIOS component, (b) measure an amount of time taken to initialize the pre-BIOS component, and (c) save the measured amount of time to the SRAM as a pre-BIOS boot-time record. Other embodiments are described and claimed.

Technology to measure boot activity before a processor enters a working state

Systems, apparatuses and methods may provide for technology that detects a low battery condition in a computing system including an integrated graphics processor and a discrete graphics processor, wherein the low battery condition is detected during a pre-boot stage of the computing system. The technology may also disable a root port associated with the discrete graphics processor in response to the low battery condition, conduct an initialization of an integrated display while the root port is disabled, and enable the root port in response to a successful negotiation of increased power by a verified read write code of an embedded controller of the computing system.

Dynamic bios policy for hybrid graphics platforms

Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code after a power on of the system.

Methods, systems, and apparatuses for a multiprocessor boot flow for a faster boot process

Embodiments are directed to a phased boot process to dynamically initialize devices in a verified environment. An embodiment of a system includes a memory device to store platform initialization firmware to cause the processing system to: initialize, during a boot process, a portion of the one or more memory modules as system management random access memory (SMRAM) for system management mode (SMM) usage; generate an SMM component in the SMRAM, the SMM component comprising an SMM handler routine to handle dynamic intellectual property (IP) management operations corresponding to the plurality of hardware components; register the SMM handler routine with an SMM interrupt (SMI) for identification of SMM events from an operating system (OS); and generate an SMM dispatcher in the SMRAM, the SMM dispatcher to create an instance of the SMM handler routine in the SMRAM in response to receiving an SMI from the OS during runtime of the processing system.

Phased boot process to dynamically initialize devices in a verified environment

Embodiments are directed to improving boot process for early display initialization and visualization. An embodiment of a system includes a plurality of processor cores; a cache coupled to the plurality of processor cores; and a controller circuit to: initialize a portion of the cache as static memory for hardware initialization code usage before beginning execution of the hardware initialization code after a power on of the hardware processor; and cause initialization of a display device to be performed using the portion of the cache, the initialization of the display device performed independently of initialization of dynamic memory of the hardware processor.

Boot process for early display initialization and visualization

Systems, apparatuses and methods may provide for technology that initiates a boot of a computing system containing an embedded controller while the computing system is in a low power mode, conducts a verification that code to perform the boot is uncorrupted, and negotiates an increased power delivery with a source device connected to the computing system if the verification is successful.

Verified high-power transition and fast charging with pre-boot scaling

A method and device that implements communication over an interconnect to support improved power distribution over the interconnect. The device includes a controller to implement a device policy manager (DPM) to manage power allotment over the interconnect, and a battery feedback mechanism coupled to the controller, the battery feedback mechanism to detect a low or dead battery condition of a connected device over the interconnect and to indicate to the DPM to advertise a higher power charging level to the connected device.

Growing community of inventors

Bengaluru, India

Rajaram Regupathy