Cavium, Inc.

Fungible, Inc.

Microsoft Technology Licensing, LLC

Cisco Technology, Inc.

Marvell Asia Pte., Ltd.

Cavium Networks, Inc.

Rajan Goyal

Satyanarayana Lakshmipathi Billa

Gregg Alan Bouchard

Kenneth A Bullis

Jeffrey Alan Pangborn

Richard Eugene Kessler

Muhammad Raghib Hussain

Najeeb Imran Ansari

Abhishek Kumar Dikshit

Pradeep S Sindhu

Jean-Marc Frailong

Deepak Goel

Wael Noureddine

Bertrand Serlet

Felix A Marti

Abhishek Dikshit

Yi-Hua Edward Yang

Edward David Beckman

Karen A Szypulski

Eric Scot Swartzendruber

Gurumani Senthil Nayakam

Gregory Edward Lund

Timothy Toshio Nakada

Troy S Dahlmann

Jeffrey Richard Hardesty

Sandipkumar J Ladhani

Ken Bullis

Yossef Shanava

Philip A Thomas

Paul Kim

Aibing Zhou

Jorge Cruz-Rios

Trent Parker

Aseem Maheshwari

Rahul Gupta

Frank Henry Worrell

Pere Monclus

Ahmed Shahid

Dan Touitou

Shyamasundar S Kaluve

Virgil Nicolae Mihailovici

Charles D Spackman

Ahsan Habib

Phillip A Thomas

Michael Zayats

Lakshmipathi Billa

Imrar Badr

M Raghib Hussain

Chris Chinchia Kuo

Kirtikumar L Prabhu

Christophe J Paggen

Kamesh Akundi

Thomas Guerrette

John Gawf

A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.

Data processing unit for stream processing

System and methods for performing analytical operations are described. A hardware-based regular expression (RegEx) engine performs a regular expression operation on a stream of data units based on a finite automata (FA) graph. Performing includes configuring a regular expression engine of a hardware-based regular expression accelerator to, beginning at a root node in the plurality of nodes of the FA graph, step the regular expression engine through one or more nodes of the FA graph until the regular expression engine arrives at a skip node and to consume, at the skip node, two or more data units from the stream of data units before traversing one of the directional arcs to another node.

Finite automata global counter in a data flow graph-driven analytics platform having analytics hardware accelerators

A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.

Data processing unit for compute nodes and storage nodes

A data flow graph-driven analytics platform is described in which highly-programmable data stream processing devices, referred to generally herein as data processing units (DPUs), operate to provide a scalable, fast and efficient analytics processing architecture. In general, the DPUs are specialized data-centric processors architected for efficiently applying data manipulation operations (e.g., regular expression operations to match patterns, filtering operations, data retrieval, compression/decompression and encryption/decryption) to streams of data units, such as packet flows having network packets, a set of storage packets being retrieved from or written to storage or other data units.

Data flow graph-driven analytics platform using data processing units having hardware accelerators

An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.

Access node for data centers

This disclosure describes techniques that include performing cryptographic operations (encryption, decryption, generation of a message authentication code). Such techniques may involve the data processing unit performing any of multiple modes of encryption, decryption, and/or other cryptographic operation procedures or standards, including, Advanced Encryption Standard (AES) cryptographic operations. In some examples, the security block is implemented as a unified, multi-threaded, high-throughput encryption and decryption system for performing multiple modes of AES operations.

Multimode cryptographic processor

This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.

Reliability coding for storage on a network

A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data processing functions. This disclosure describes a programmable hardware-based data compression accelerator that includes a pipeline for performing static dictionary-based and dynamic history-based compression on streams of information, such as network packets. The search block may support single and multi-thread processing, and multiple levels of compression effort. To achieve high-compression, the search block may operate at a high level of effort that supports a single thread and use of both a dynamic history of the input data stream and a static dictionary of common words. The static dictionary may be useful in achieving high-compression where the input data stream is relatively small.

Static dictionary-based compression hardware pipeline for data compression accelerator of a data processing unit

A system comprises a data processing unit (DPU) integrated circuit having programmable processor cores and hardware-based accelerators configured for processing streams of data units; and software executing on one or more of the processing cores. In response to a request to perform an operation on a set of one or more data tables, each having one or more columns of data arranged in a plurality of rows, the software configures the DPU to: input at least a portion of the rows of each of the database tables as at least one or more streams of data units, process the one or more streams of data units with the hardware-based accelerators to apply one or more of compression, encoding or encryption to produce a resultant stream of data units; and write the resultant stream of data units to a storage in a tree data structure.

Data ingestion and storage by data processing unit having stream-processing hardware accelerators

A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes examples of retrieving values represented by one or more previous symbols needed for decoding a current symbol before or in parallel with the insertion of the values represented by the one or more previous symbols in the data stream.

Context value retrieval prior to or parallel with expansion of previous symbol for context-decoding in range decoder

A hardware-based programmable deep learning processor (DLP) is proposed, wherein the DLP comprises with a plurality of accelerators dedicated for deep learning processing. Specifically, the DLP includes a plurality of tensor engines configured to perform operations for pattern recognition and classification based on a neural network. Each tensor engine includes one or more matrix multiplier (MatrixMul) engines each configured to perform a plurality of dense and/or sparse vector-matrix and matrix-matrix multiplication operations, one or more convolutional network (ConvNet) engines each configured to perform a plurality of efficient convolution operations on sparse or dense matrices, one or more vector floating point units (VectorFPUs) each configured to perform floating point vector operations, and a data engine configured to retrieve and store multi-dimensional data to both on-chip and external memories.

Systems and methods for deep learning processor

An example integrated circuit includes a memory including a non-deterministic finite automata (NFA) buffer configured to store a plurality of instructions defining an ordered sequence of instructions of at least a portion of an NFA graph, the portion of the NFA graph comprising a plurality of nodes arranged along a plurality of paths. The NFA engine determines a current symbol and one or more subsequent symbols of a payload segment that satisfy a match condition specified by a subset of instructions of the plurality of instructions for a path of the plurality of paths and in response to determining the current symbol and the one or more subsequent symbols of the payload segment that satisfy the match condition, outputs an indication that the payload data has resulted in a match.

Instruction-based non-deterministic finite state automata accelerator

Growing community of inventors

Saratoga, CA, United States of America

Rajan Goyal