Cadence Design Systems, Inc.

Rajan Arora

Arnold Ginetti

Gilles S C Lamant

Chayan Majumder

Randy Bishop

Sandipan Ghosh

Anil Kumar Arya

Pawan Fangaria

Arnold Jean-Marie Gustave Ginetti

Gautam Kumar

Umesh Sisodia

Anurag Jain

Methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user.

Methods, systems, and computer-program products for item selection and positioning suitable for high-altitude and context sensitive editing of electrical circuits

A system, method, and computer program product for automatically placing contact cuts in integrated circuit layouts, particularly in guard rings, inter-layer via connections, and various space-filling structures typically defined by polygons or paths. Areas to be filled with contact cuts are partitioned horizontally and vertically, and decomposed into shared and exclusive type regions that are sorted directionally. Contact cuts are placed in each region according to its type and according to relevant design rules on contact cut spacing and enclosure constraints. Contact cuts that may cause design rule violations are deleted. Narrow jogs or cuts, merged shared regions, and non-orthogonal edges or segments in the decomposed regions are handled by alternate embodiments. The result is automated contact cut placement, even for merged/chopped layout features, that is generally more symmetric, collinear, and adds an optimal number of contact cuts in most cases than with existing tools.

System and method for automatic placement of contact cuts and similar structures in integrated circuit layouts

An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counter(s). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data.

Method and system for implementing multiuser cached parameterized cells

Embodiments of the invention provide system and methods for EDA tools. Specifically, some embodiments of the invention provide an input infrastructure for EDA tools that gathers pertinent information surrounding an input cursor's present locality (or neighborhood) and then analyzes the pertinent information in view of an issued command to automatically determine suitable targets or subsequent operations that a user of the EDA tool may want to select next.

System and method for aperture based layout data analysis to achieve neighborhood awareness

An improved method and system are disclosed for utilizing abstracted versions of layout portions in conjunction with parameterized cells (pcells). One significant advantage is that abstracted versions of pcells can be generated from normal pcells and stored in a pcell cache, which avoids the need to abstract layout pcells on the fly.

Method and system for implementing abstract layout structures with parameterized cells

An improved method, system, computer program product, and electronic design structures which provides the flexibility to IC designers to be able to relax the design rules to increase the yield and improve the layout productivity is disclosed. In some disclosed approaches, automated interactive aids and batch tools are provided which can assist in optimizing the final layouts for yield at the initial placement and/or routing stages for optimizing yield. Provided in some disclosed approaches are automated capability to layout designers at the mos devices level to configure mos devices as per different DFY recommendations from the foundry without negative effects on the overall chip area (or cell size). The design rules may be relaxed selectively on an instance basis and wherever possible or desirable.

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Faridabad, India

Rajan Arora