Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Rajamohan Varambally

Piero Capocelli

Andrea Baroni

Michele Taliercio

Luigi Carro

Giovanni Mastrodomenico

Taliercio Michele

A memory device generator for generating memory devices in a CAD environment, the generator composed of a library file containing predefined basic circuit components; memory array generation algorithm interacting with the library file for generating a variable-size memory array representation having a variable number of memory elements, and at least one redundant memory element; memory element selection circuit generation algorithm interacting with the library file for generating a memory element selection circuit to be associated with the memory array for selecting at least one memory element according to memory device address inputs. The memory element selection circuit generation algorithm having a subroutine for generating a variable-size content-addressable memory representation having a plurality of content-addressable memory locations each one associated to a respective memory element or to a redundant memory element, each of the content-addressable memory locations suitable for storing one of a set of values of the memory device address inputs and for selecting the respective memory element or redundant memory element when the memory device address inputs take the one value.

Memory device generator for generating memory devices with redundancy

A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

High performance single port RAM generator architecture

A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure. The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

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Karnataka, India

Rajamohan Varambally