Apple Inc.

Advanced Micro Devices Corporation

Ati Technologies Ulc

Ati Technologies Inc.

Rajabali M Koduri

Ian C Hendry

Khaled Mammou

Gabor Sines

David I Glen

Lei Zhang

Bruce Montag

Layla A Mah

Jeffry E Gonion

Ronald Nadim Isaac

Andrew S Pomianowski

Niel David Warren

Matthew Xavier Mora

David A Gotwalt

Changki Min

Brett D George

David A Leech

Gordon M Elder

Jeffrey A Golds

A device and method for processing Virtual Reality (VR) data is disclosed. The method comprises transmitting feedback information from the device to a server, wherein the feedback information is captured in the device, receiving data from the server to be presented on the device based on the feedback information, wherein the data includes video data and audio data where the video data is a frame of video data in a sequence of frames and the audio data is the corresponding audio data of the frame, decoding the video data and corresponding audio data of the frame, and controlling the presentation of the video data and corresponding audio data on the device such that the video data is synchronized with the corresponding audio data.

Low latency wireless virtual reality systems and methods

Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (A/V) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.

Low latency wireless Virtual Reality systems and methods

Virtual Reality (VR) systems, apparatuses and methods of processing data are provided which include predicting, at a server, a user viewpoint of a next frame of video data based on received user feedback information sensed at a client, rendering a portion of the next frame using the prediction, encoding the portion, formatting the encoded portion into packets and transmitting the video data. At a client, the encoded and packetized A/V data is received and depacketized. The portion of video data and corresponding audio data is decoded and controlled to be displayed and aurally provided in synchronization. Latency may be minimized by utilizing handshaking between hardware components and/or software components such as a 3D server engine, one or more client processors, one or more client processors, a video encoder, a server NIC, a video decoder, a client NIC; and a 3D client engine.

Methods and apparatus for processing media signals. In one embodiment, a data processing device processes fixed and variable rate data using a first and second processing unit. The processing comprises real-time processing of audio/video signals by a graphics processing unit (GPU) and/or central processing unit (CPU). The processing units process data efficiently by establishing one processor as always processing variable rate data, and using one or more schemes for determining processor will process fixed rate data. A shared memory enables the processors to communicate with one another in order to determine which will process the fixed rate data. In one scheme for determining which of the processors will process the fixed rate data the second processor need merely be unlocked. In another embodiment, the second processor must be unlocked and immediately available.

Apparatus and methods for processing of media signals

Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.

Memory controller mapping on-the-fly

The disclosed embodiments provide a system that drives a display from a computer system. During operation, the system detects an idle state in a first graphics-processing unit (GPU) used to drive the display. During the idle state, the system switches from using the first GPU to using a second GPU to drive the display and places the first GPU into a low-power state, wherein the low-power state reduces a power consumption of the computer system.

Low-power GPU states for reducing power consumption

Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity.

Coherent memory scheme for heterogeneous processors

A processing unit, method, and graphics processing system are provided for processing a plurality of frames of graphics data. For instance, the processing unit can include a first plurality of graphics processing units (GPUs), a second plurality of GPUs, and a plurality of compositors. The first plurality of GPUs can be configured to process a first frame of graphics data. Likewise, the second plurality of GPUs can be configured to process a second frame of graphics data. Further, each compositor in the plurality of compositors can be coupled to a respective GPU from the first and second pluralities of GPUs, where the plurality of compositors is configured to sequentially pass the first and second frames of graphics data to a display module.

Video processing across multiple graphics processing units

A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.

Growing community of inventors

Cupertino, CA, United States of America

Rajabali M Koduri