Texas Instruments Corporation

Raja Selvaraj

Thomas Dyer Bonifield

Byron Lovell Williams

Anant Shankar Kamath

John Kenneth Arch

Subhashish Mukherjee

Venugopal Gopinathan

Jayateerth Pandurang Mathad

Sujay Kumar

Sachin Ishwar Gojagoji

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

Device isolator with reduced parasitic capacitance

An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.

Integrated circuit with single level routing

An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

Methods and apparatus for scribe seal structures

An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include methods of forming an integrated circuit including an isolator structure. The isolator structure includes parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator

A method and apparatus for fabricating integrated circuits providing a desired operation using a plurality of masks, wherein each of said plurality of masks is used to control a corresponding one of a plurality of layers to form said integrated circuits. Said method includes incorporating a plurality of dummy stacks along with a functional block, said functional block providing said desired operation, each of said dummy stack providing a point of common connectivity on a plurality of metal layers comprised in said plurality of layers.

Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit

Dummy stacks, each providing a common point of connectivity potentially across all metal layers, are incorporated along with the functional block in an integrated circuit. When the connectivity of elements of the functional block need to be changed later, the dummy stacks enable masks, which would otherwise need to be redesigned, to be further redesigned to obtain the desired connectivity. As a result, the redesign of some of the other masks, may be avoided, thereby reducing the total number of masks which would need to be redesigned while effecting a change in the connectivity of elements in a functional block.

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Bengaluru, India

Raja Selvaraj