Cadence Design Systems, Inc.

Raja Mitra

Abdelhakim Bouamama

Jun Chen

Jian Wang

Hao Ji

The present disclosure relates to a computer-implemented method for parasitic extraction. The method may include providing, using one or more processors, an electronic design having IP and/or metal fill content associated therewith. The method may further include identifying at least one layer associated with the content to be modeled and identifying at least one layer associated with the content to be ignored. The method may also include discarding one or more shapes associated with the at least one layer associated with the content to be modeled and replacing each discarded shape with an alternative shape. The method may further include modeling the electronic design including the alternative shape, wherein modeling is electrically aware in a horizontal and a vertical direction. The method may further include a spatial modeling approach where non-extractable shapes are exclusively grouped across the design area including multiple layers, keeping configurable spatial separation between neighboring extractable shapes.

System and method for electrically and spatially aware parasitic extraction

An approach is described for efficient and accurate signal electromigration analysis of digital-on-top designs with complex interface pin shapes. According to some embodiments, the approach includes performance of parasitic analysis for the interface between nets and primitive/macro cell (blocks). Specifically, the approach includes performing parasitic analysis based on actual location information corresponding to overlap/connection between ports within blocks, external net connections to the ports, and internal net (block net) connections to the port. Thus, by determining the actual locations of the connections (as opposed to a presumed location) the parasitic effects associated with the ports and the connections thereof can be calculated.

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Cupertino, CA, United States of America

Raja Mitra