Advanced Micro Devices Corporation

Microsoft Technology Licensing, LLC

Globalfoundries Inc.

Microsoft Technology Holding, LLC

Raj N Master

Mohammad Zubair Khan

Seah Sun Too

Maria G Guardado

Jonathan D Halderman

Michael Joseph Lane

Mohammad A Khan

Maxat Touzelbaev

Paul Bornemann

Ajit M Dubey

Frank G Kuechenmeister

Mark Thomas McCormack

Jacquana T Diep

Janet Kirkland

Tek Seng Tan

Hsiang Wan Liau

Srinivasan Parthasarathy

Orion K Starr

Ralf Groene

Jun Zhai

James Alec Ishihara

Dennis W Tom

Farah Shariff

Joshua James Fischer

Krishna Darbha

Edward S Alcid

Charles Anderson

Ranjit Gannamani

Terri J Brownfield

David Bruce Morken

Ooi Tong Ong

Ahmad Juwanda

Ong Ot

C S Chan

Ot Ong

Diong Hing Ding

Junaida Abu Bakar

Sofi Mohd

Sp Lee

Junaida A Bakar

L K Teoh

Anthony Allen Fischer

Diong H Ding

Loo L Teoh

Zulfiqar Alam

Srinivasan Ashok Anand

Yew Cheong Mui

Diong-Hing Ding

Chan Cs

Mark Thomas Mccormack

Dennis Tom

Paul C Bornemann

Techniques for graphic formation via material ablation described. In at least some implementations, a graphic is applied to a surface of an object by ablating layers of the object to form an ablation trench in the shape of the graphic. In at least some embodiments, an object can include a surface layer and multiple sublayers of materials. When an ablation trench is generated in the object, the ablation trench can penetrate a surface layer of the object and into an intermediate layer. In at least some implementations, height variations in an object surface caused by an ablation trench can cause variations in light reflection properties such that a graphic applied via the ablation trench appears at a different color tone than a surrounding surface, even if the ablation trench and the surrounding surface are coated with a same colored coating.

Graphic formation via material ablation

An electronic device includes an electronic component configured to receive electric current and a plated contact electrically coupled to the electronic component and configured to carry the electric current to the electronic component from a system external to the device. The plated contact includes a copper-alloy layer, a platinum-group metal (PGM) layer plated over the copper-alloy layer, and a gold-alloy layer plated over the PGM layer.

Electronic device with plated electrical contact

Metal alloy injection molding techniques are described. In one or more implementations, these techniques may also include adjustment of injection pressure, configuration of runners, and/or use of vacuum pressure, and so on to encourage flow of the metal alloy through a mold. Techniques are also described that utilize protrusions to counteract thermal expansion and subsequent contraction of the metal alloy upon cooling. Further, techniques are described in which a radius of edges of a feature is configured to encourage flow and reduce voids. A variety of other techniques are also described herein.

Metal alloy injection molding

Metal alloy injection molding overflows

Metal alloy injection molding protrusions

Various sockets for packaged integrated circuits and methods of making the same are provided. In one aspect, a method of mounting a semiconductor chip is provided that includes providing a package that has a base substrate with a first side and a second side opposite the first side. The second side has a central region. The package includes a semiconductor chip and a lid coupled to the first side. A socket is provided for receiving the base substrate. The socket includes a mound that projects toward the second side of the base substrate when the base substrate is seated in the socket to provide support for the central region of the base substrate. The package is mounted in the socket. The mound provides support for the central region of the base substrate.

Integrated circuit socket

Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.

Void reduction in indium thermal interface material

Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6.0 10K.

Semiconductor chip with solder joint protection ring

Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes placing a gel-type thermal interface material in a preselected pattern on a semiconductor chip that is coupled to a substrate. The preselected pattern of gel-type thermal interface material is allowed to partially set up. Additional thermal interface material is placed on the semiconductor chip and cured.

Method for decreasing surface delamination of gel-type thermal interface material by management of the material cure temperature

Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes forming a metal layer on a semiconductor chip and forming a gel-type thermal interface material layer on the metal layer. A solvent and a catalyst material are applied to the metal layer prior to forming the gel-type thermal interface material layer to facilitate bonding between the gel-type thermal interface material layer and the metal layer.

Semiconductor device with gel-type thermal interface material

A method for forming a solder joint for a package arrangement with a dispersed Sn microstructure provides a flip chip on a package, with a flip chip having solder bumps to be connected by eutectic solder joints to pads on the package. The eutectic solder is reflowed at a solder bump/pad interface with a eutectic reflow profile that is configured to achieve eutectic solder joints having substantially evenly distributed Sn grains. The eutectic reflow profile includes an increased cooling rate and decreased hold time with a higher peak temperature. A defined ratio of the pad openings in the solder mask to the under bump metallurgy is provided. The eutectic reflow profile and the defined ratio prolong fatigue life in the package arrangement.

Method for forming solder joints for a flip chip assembly

Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.

Reduction of damage to thermal interface material due to asymmetrical load

A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximately 4 wt % to approximately 8 wt % bismuth, approximately 2 wt % to approximately 4 wt % silver, approximately 0 wt % to approximately 0.7 wt % copper, and approximately 87 wt % to approximately 92 wt % tin. The die solder pads might comprise between approximately 7 wt % to approximately 20 wt % indium, between approximately 2 wt % to approximately 4.5 wt % silver, between approximately 0 wt % to approximately 0.7 wt % copper, between approximately 0 wt % to approximately 0.5 wt % antimony, and between approximately 74.3 wt % to approximately 90 wt % tin.

Lead-free semiconductor package

Growing community of inventors

San Jose, CA, United States of America

Raj N Master