Intel Corporation

Qualcomm Incorporated

Sandisk Technologies Inc.

Raj K Ramanujan

Francesc Guim Bernat

Karthik Kumar

Glenn J Hinton

Thomas Willhalm

Robert G Blankenship

Muthukumar Swaminathan

Debendra Das Sharma

Taarinya Polepeddi

Mohan J Kumar

Yen-Cheng Liu

David Zimmerman

Brian J Slechta

Mark A Schmisseur

Arvind A Kumar

Venkatraman Iyer

Rajat Agarwal

Simon P Johnson

Bill Nale

Robert J Safranek

Herbert H Hum

Tessil Thomas

Darren S Jue

Ashish Gupta

Vedaraman Geetha

Bahaa Fahim

Aaron T Spink

Jeffrey Charles Swanson

Fulvio Spagna

Rahul R Shah

Robert H Beers

Jeff Willey

Sitaraman V Iyer

William Harry Nale

Abhishek Das

Yuvraj S Dhillon

Robert A Maddox

Mohamed Arafa

Kuljit Singh Bains

Kai Cheng

Narayan Ranganathan

Eric Dahlen

Dimitrios Ziakas

Bassam N Coury

Liyong Wang

Camille C Raad

Wesley Queen

Kshitij Arun Doshi

Rajesh M Sankaran

Ward M Parkinson

Daniel Rivas Barragan

Balint Fleischer

Gilbert A Neiger

Michael Grobis

Joseph Nuzman

John H Crawford

Richard Paul Mangold

Robert S Chappell

Brian S Morris

Nathan Franklin

Leena K Puthiyedath

Michael Nicolas Albert Tran

Sreenivas Mandava

Martin P Dimitrov

Vincent J Zimmer

David M Durham

Michael A Rothman

Ravi L Sahita

Jun Zhu

David J Harriman

Richard A Uhlig

Jawad Basit Khan

Murugasamy K Nachimuthu

Andrew J Herdrich

Blaise B Fanning

Kiran Pangal

Rajesh Sundaram

Martin Aureliano Hassner

Sanjay Kumar

Parthasarathy Sarangam

Won Ho Choi

Martin Lueker-Boden

Robert W Faber

Sailesh Kottapalli

Theodros Yigzaw

David M Lee

Rajesh S Parthasarathy

Larisa Novakovsky

Arun Raghunath

Ishwar Agarwal

Adrian C Moga

Woojong Han

Steen K Larsen

Subramanya R Dulloor

Wayne Alan Downer

Charles A Giefer

Madhavan Parthasarathy

Larry O Smith

Gaspar Mora Porta

Ningde Xie

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

High performance interconnect

Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.

Technologies for quality of service based throttling in fabric architectures

Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.

Mixed current-forced read scheme for MRAM array with selector

Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).

Programmable ECC for MRAM mixed-read scheme

An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

Memory card with volatile and non volatile memory space having multiple usage model configurations

Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.

Apparatus and method for performing persistent write operations using a persistent write command

Generally discussed herein are systems, devices, and methods for prefetcher in a multi-tiered memory (DSM) system. A node can include a network interface controller (NIC) comprising system address decoder (SAD) circuitry configured to determine a node identification of a node to which a memory request from a processor is homed, and prefetcher circuitry communicatively coupled to the SAD circuitry, the prefetcher circuitry to determine, based on an address in the memory request, one or more addresses from which to prefetch data, the one or more addresses corresponding to respective entries in a memory of a node on a different network than the NIC.

Prefetcher in multi-tiered memory systems

Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface logic to interface with a communication module using a bidirectional interconnect link compliant with a peripheral component interconnect express (PCIe) protocol. The interface logic to receive a data packet from across the link, the data packet comprises a header and data payload; determine a hint bit set in the header of the data packet; determine a steering tag value in the data packet header based on the hint bit set; and transmit the data payload to non-volatile memory based on the steering tag set in the header.

Persistent memory write semantics on PCIe with existing TLP definition

A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.

Dynamic partial power down of memory-side cache in a 2-level memory hierarchy

A processing system for performing persistent write operations comprises a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host. Persistent Write completion indications may be provided to the host in a different order from an order in which corresponding commands were received. Statuses of Persistent Write commands may be maintained in a completed bitmap or a pending bitmap. A FLUSH command may be provided to indicate that all prior writes buffered in volatile media are to be pushed to non-volatile or persistent memory. The memory system may include a non-volatile dual in-line memory module which supports Persistent Writes (NVDIMM).

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Federal Way, WA, United States of America

Raj K Ramanujan