Other

International Business Machines Corporation

Raj Jammy

Helmut Horst Tews

Ulrike Gruening

Stephan Kudelka

Uwe Paul Schroeder

Alexander Michaelis

Oleg Gluschenkov

Michael Patrick Chudzik

Uwe Schroeder

Brian S Lee

John Faltermeier

A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the < > crystallographic plane and another one of such planes being the < > plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the < > plane being oxidized at a higher rate than sidewalls in the < > plane producing silicon dioxide on the silicon nitride layer having thickness over the < > plane greater than over the < > plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the < > plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the < > plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the < > plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the < > plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

Semiconductor structures and manufacturing methods

A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the <100> crystallographic plane and another one of such planes being the <1 10> plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the <110> plane being oxidized at a higher rate than sidewalls in the <100> plane producing silicon dioxide on the silicon nitride layer having thickness over the <110> plane greater than over the <100> plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the <100> plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the <110> plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the <100> plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the <110> plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

Method of forming low-leakage on-chip capacitor

A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer. The second dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness and the second thickness of the second dielectric layer are closer in thickness than the first thickness and the second thickness of the first dielectric layer due to the implantation of the dopants.

Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates

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Wappingers Falls, NY, United States of America

Raj Jammy