International Business Machines Corporation

Rainer Zuehlke

Helmut Schettler

Volker W Zimmermann

Otto M Wagner

Hartmut Ulland

Hans Schumacher

Rudolf Brosch

Kurt Pollmann

Heinz Lutz

Klaus Klein

Uwe Schulz

For the physical design of a very large scale integration (VSLI) chip, a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology, the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus, the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.

Method for physical VLSI-chip design

For equalizing the signal delay times of semiconductor chips a digital control circuit is provided on each chip. By altering the supply voltage, the digital control circuit influences the signal delay times. The digital control circuit comprises a comparator circuit where the signal delay of a clock pulse is compared in a chain of inverters with the very precisely defined clock interval. Depending on the result of the comparison, the count of an up-down counter is incremented or decremented by one. The resulting count is decoded and converted into a corresponding voltage for operating the circuits of the semiconductor chip. Subsequently, the above described steps are repeated until the difference .DELTA.t between the arrival of a clock pulse delayed by the chain, and the following undelayed clock pulse approaches zero.

Method and circuitry for equalizing the differing delays of

An improved method and apparatus for determining the speed and position values of a stepping motor for controlling or regulating the same. These values are derived from induced voltages within the bifilar windings of the stepping motor combined with voltages across and currents through the same bifilar windings. The speed values are derived from the amplitude of the induced voltages and the position values are derived from the zero transitions of the induced voltages. A desirable advance of the motor is distinguished from an undesirable oscillation of the motor by determining whether the induced voltages in the bifilar windings become zero simultaneously.

Method and apparatus for determining stepping motor parameters from

A rotor stator assembly comprising a stepping motor having an improved torque-to-inertia ratio resulting from a substantial reduction in moment of inertia due to the conical shape of the rotor. A core energized by a DC coil is disposed axially of the base of the conical rotor and the magnetic path is through the base of the rotor, out its periphery, through the stator, through conductive members and back to the core. There is a further increase in torque-to-inertia ratio which is due to a decrease in rotating mass when the rotor is hollow.

Rotor stator assembly for a low inertia stepping motor

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Warmbronn, Germany

Rainer Zuehlke