Infineon Technologies Ag

Rainer Steiner

Jens G Pohl

Gottfried Beer

Werner Robl

Michael Bauer

Hans-Joachim Barth

Mathias Vaupel

Holger Woerner

Markus Brunnbauer

Hermann Vilsmeier

Joern Plagmann

Ulrich Bachmaier

Bernhard Zuhr

Peter Strobel

Robert-Christian Hagen

Udo Ausserlechner

Joachim Mahler

Horst Theuss

Edward Fuergut

Khalil Hosseini

Georg Meyer-Berg

Jochen Dangelmaier

Volker Strutz

Georg Ernst

Christian Birzer

Holger Wörner

Robert Christian Hagen

Joem Plagmann

Hermann Vllsmeler

A current sensor device includes a casing having a cavity and a conductor fixedly mounted to the casing. A semiconductor chip configured to sense a magnetic field is arranged in the cavity. An electrically insulating medium is configured to at least partially fill the cavity of the casing.

Current sensor device

In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Chip arrangement and a method of manufacturing a chip arrangement

One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.

Semiconductor structure and method for making same

One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.

A semiconductor stack and a semiconductor base device with a wiring substrate and an intermediate wiring board for a semiconductor device stack is disclosed. In one embodiment, a semiconductor chip is arranged between the intermediate wiring board and the wiring substrate, which is electrically connected by way of the wiring substrate on the one hand to external contacts on the underside of the wiring substrate and on the other hand to contact terminal areas in the edge regions of the wiring substrate. The intermediate wiring board has angled-away external flat conductors, which are electrically connected in the contact terminal areas of the wiring board. Furthermore, on the upper side of the intermediate wiring board, arranged on the free ends of the internal flat conductors are external contact terminal areas, which correspond in size and arrangement to external contacts of a semiconductor device to be stacked.

Semiconductor device stack and method for its production

A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.

Device fabricated using an electroplating process

A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.

Semiconductor device including molding compound layer forms a common plane with the surface of the semiconductor chip

One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.

A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.

Semiconductor device including conductive element

Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound

A semiconductor component includes a plastic housing including: plastic outer surfaces; lower outer contact surfaces arranged on an underside of the housing; upper outer contact surfaces arranged on a top side of the housing that is opposite the underside; and outer interconnects electrically connecting the lower outer contact surfaces to the upper outer contact surfaces, the outer interconnects including a layer of solder arranged on conduction paths along an outer contour of the housing.

Semiconductor component with plastic housing, and process for producing the same

A wiring substrate of a semiconductor component includes: an underside with a wiring structure; a top side with cutouts; a rubber-elastic material arranged in the cutouts; and external contact pads arranged on the rubber-elastic material and configured to be coupled to external contacts. A method for producing a wiring substrate of this type, involves pressing the rubber-elastic material pads into a precursor of a polymer plastic during the production process.

Wiring substrate of a semiconductor component comprising rubber-elastic pads embedded in said wiring substrate and method for producing the same

The invention relates to an electronic component with a housing package comprising a number of layers of plastic with at least one buried interconnect layer and with at least one semiconductor chip, which has pointed-conical external contacts distributed on an outer side. The pointed-conical external contacts penetrate through one of the layers of plastic and form contact vias with respect to the buried interconnect layer. Furthermore, the invention relates to a method for producing such an electronic component.

Growing community of inventors

Wuppertal, Germany

Rainer Steiner