International Business Machines Corporation

Rainer Stahl

Helmut Schettler

Erich Klink

Thomas Ludwig

Otto M Wagner

Werner O Haug

Karl E Kroll

Rainer Zuhlke

Horst Krumm

Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor. At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

Integrated circuit package

Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor. At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

Disclosed is a multi-layer module structure having a constant characteristic impedance. In each conductor line plane, two signal lines are arranged between a ground and a voltage supply line. This line sequence: ground/signal/signal/voltage supply line, is repeated several times in each conductor line plane. The spacing between the signal line and the adjacent ground and voltage supply line, respectively, is identical in each case. Adjacent conductor line planes, nth and (n+1)th have conductor lines arranged orthogonally. The lines of the nth and the (n+2)th plane are preferably staggered to each other such that when the nth plane is projected relative to the (n+2)th plane, the ground line of the (n+2)th plane is arranged in between the voltage supply lines (e.g. a voltage supply line and a ground line) of the nth plane.

Multi-layer module with constant characteristic impedance

Growing community of inventors

Schonaich, Germany

Rainer Stahl