Deutsche Itt Industries Gmbh

Rainer Schweer

Soenke Mehrgardt

Heinrich Pfeifer

A digital delay arrangement generates a delay time which is a noninteger multiple of the period of a system clock frequency. The arrangement includes a digital delay circuit having a delay time equal to the period, a multiplier for the part of the noninteger multiplier, b, being less than one, a further multiplier for 1- b, an adder and a peaking filter clocked by the system clock.

Delay circuit for digital signals

A digital frequency demodulator circuit works on the principle of determining the number of zero crossings of a band-limited input signal in a given period of time, in corresponding prior art analog circuits. The circuit includes an analog-to-digital converter, three delay elements, two edge detectors, an up/down counter, two arcsin read-only memories, a 1/2 multiplier and a multiple adder.

Frequency demodulator circuit with zero-crossing counter

To achieve improved and, in particular, optimum deflection correction of television picture tubes the sawtooth signal from the horizontal or vertical oscillator which is conventionally subjected to a correction, is left uncorrected. Per line, the time relation of the digital video signal controlling the picture tube via digital-to-analog converters is changed with respect to the time relation of the video signals as reconditioned with the aid of a video processor, i.e., by the correcting value depending on the respective locus of an image spot on the screen. Accordingly, the deflection correction is not carried out by influencing deflection means, but by a corresponding correction of the time relation of the video signals with respect to their loci on the picture screen.

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Waldkirch, Germany

Rainer Schweer