Siemens Aktiengesellschaft

Siemens Aktiengesell Schaft

Siemens Aktiengelsellschaft

Rainer Kraus

Kurt Hoffmann

Oskar Kowarik

Manfred Paul

Hans-Dieter Oberle

Bernhard Lustig

Hans D Oberle

An integrated semiconductor circuit includes word lines and bit lines. A memory region has at least one memory cell field with memory cells addressable through the word lines and the bit lines, and a number of evaluator circuits corresponding to the number of the bit lines. Each of the evaluator circuits is connected with one of the bit lines and divides the one bit line into two at least approximately identical bit line halves. Logic units of a block perform digital processing of data read-out of the memory region through the bit lines and evaluated. Each of the logic units is connected to the two bit line halves of one of the bit lines. Various operating modes of the block of logic units are selected with mode select signals.

Integrated semiconductor circuit

An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.

Integrated semiconductor memory

A band gap reference circuit configuration includes first and second bipolar transistors having base-to-emitter voltages. An emitter resistor is connected to the first bipolar transistor. An operational amplifier is connected to the bipolar transistors for processing a difference generated between the base-to-emitter voltages of the first and second bipolar transistors to generate a largely temperature-independent reference voltage. The bipolar transistors are parasitic transistors, and the operational amplifier is constructed in MOS technology.

CMOS band gap reference circuit

An integrated semiconductor memory of the DRAM type includes word lines and bit line pairs. Memory cells in a matrix are connected to the word lines and the bit lines. One evaluator circuit per bit line pair is connected to the bit lines. Each of the bit line pairs is divided into one bit line and one reference bit line during operation. A control line is provided. At least one coupling capacitor is provided for each of the bit lines and each of the reference bit lines having a first lead connected to the bit line pair and a second lead connected to the control line. A method for testing an integrated semiconductor memory of the DRAM type includes reading data stored in memory cells out of the memory cells, precharging bit line pairs to a precharge level before reading out, and feeding an additional potential to each bit line pair after precharging.

Integrated semiconductor memory of the dram type and method for testing

Gate circuit having MOS transistors

A circuit configuration and method for testing storage cells of an integrated semiconductor memory precharges a pair of external bit lines to mutually complementary logic levels. All of the storage cells of a word line are always read-out in parallel. In a 'no fault' situation the pair of external bit lines retains its precharge level, whereas in the case of a fault, the level of the external bit line which is precharged to logical 1 falls. This is recognized by a discriminator circuit and analyzed.

Circuit configuration and a method of testing storage cells

A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which the separable connection is severed and intact, as well as at least one charging transistor, comprising, in each of the decoder stages, an addressing circuit connected to and between the switching transistor and the separable connection of the respective decoder stages, the addressing circuit being electrically simulatable when the respective separable connection is in the intact condition thereof.

Testable redundancy decoder of an integrated semiconductor memory

A multi-stage integrated decoder device has a special function which facilitates the simultaneous activation of a plurality and as many as all of its outputs. When it is used as a bit line decoder it is thus possible to activate a plurality and as many as all of the bit lines (including any redundant bit lines) of a block of storage cells of a semiconductor memory.

Multi-stage integrated decoder device

In a circuit configuration and a method for testing storage cells, all of the bit lines lead to one pair of fault lines which is first precharged with mutually-complementary logic levels. All of the storage cells of a word line are always read-out in parallel relative to one another. In the event of 'no fault' the pair of fault lines retains its logic states, whereas in the case of a fault one of the fault lines changes its logic state through switching transistors. This is recognized and analyzed by a comparator circuit in the form of an XOR-circuit or an XNOR-circuit.

Circuit configuration and a method for the testing of storage cells

A method and circuit configuration for the parallel input of data items in the form of a test pattern into a block of a semiconductor memory having a plurality of storage cells. For test purposes, data items are simultaneously input in parallel into the storage cells.

Method and circuit configuration of the parallel input of data into a

A multi-stage, integrated decoder device includes a special function which facilitates the simultaneous activation of a plurality or as many as all of its outputs while gating out a pre-selectible output. When used as bit line decoder, it is thus possible to activate a plurality or up all of the bit lines (including any redundancy bit lines) of a block of storage cells of a semiconductor memory, excluding a bit line assumed to contain at least one defective storage cell.

Multi-stage, integrated decoder device having redundancy test enable

An integrable evaluating circuit includes a trigger circuit, a first and a second circuit node, both of which serve both as inputs and as mutually-complementary outputs for the trigger circuit, a pair of signal lines exhibiting the same potential in a rest state, switching transistors each being connected between a respective one of the two circuit nodes and a respective signal line of the pair of signal lines, and a signal-enhancement circuit connected between the trigger circuit and the pair of signal lines. A signal occurring on a given one of the two signal lines is initially connected with its signal deviation to the circuit node connected to the given signal line. The switching transistor connected to the given one of the two signal lines is then blocked and cuts off the signal from the circuit node connected to the given signal line. The signal-enhancement circuit then increases the potential at the circuit node connected to the given signal line by a given amount while simultaneously reducing the potential at the other of the two circuit nodes as a result of potential shift. The potential of the circuit node connected to the given signal line is reduced and the potential of the other of the two circuit nodes is increased if the signal has a negative signal deviation.

Integrable evaluating circuit

A digital amplifier configuration in integrated circuits for the amplification of a voltage change includes a digital amplifier. The digital amplifier couples pairs of bit lines extended beyond the permissible capacity thereof to extensions of the pairs of bit lines.

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Munich, Germany

Rainer Kraus