Arm Limited

Cambridge Silicon Radio Limited

Qualcomm Technologies International, Ltd.

Rainer Herberholz

Peter Andrew Rees Williams

Amit Chhabra

David Vigar

Ludovic Oddoart

Oded Golombek

Richard Andrew Paterson

Einat Luko

George McNeil Lattimore

Anthony Lawrence McFarthing

Erik David Lindskog

Supreet Jeloka

Simon Chang

Alexander Klimov

Hong Wan

Yannis Jallamion-Grive

Luca Milani

Justin Penfold

Jeffrey Scott Boyer

Narayan Prasad Ramachandran

Kwangseok Han

Howard Godfrey

Danny Joseph Traynor

Various implementations described herein are related to a device having a first coil-shaped spiral structure for an active shield and a second coil-shaped spiral structure that is wound in-between windings of the first coil-shaped spiral structure. The first coil-shaped spiral structure may provide for a coil-based electro-magnetic (EM) shield as a counter-measure circuit for protecting an underlying circuit.

Active shield structure

Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.

Multi-dimensional network interface

Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.

Sensor for performance variation of memory read and write characteristics

Embodiments of the present disclosure advantageously provide a secure boot integrity verification system that is protected against future quantum attacks without relying on correctly functioning hardware security modules (HSMs) for the expected lifetime of the computer system or embedded device.

Secure boot process for a computer system

Disclosed are methods, systems and devices for storing states in a memory in support of applications residing in a trusted execution environment (TEE). In an implementation, one or more memory devices accessible by a memory controller may be shared between and/or among processes in an untrusted execution environment (UEE) and a TEE.

Method, system and circuit for managing a secure memory partition

Disclosed are methods, systems and devices for implementing built-in self-test (BIST) to be performed by an untrusted party and/or in an unsecure testing environment. In an embodiment, a test access port (TAP) on a device may enable a party to initiate execution of one or more BIST procedures on the device. Additionally, such a TAP may enable loading of encrypted instructions to be executed by one or more processors formed on a device under test.

Method and/or system for testing devices in non-secured environment

A monitoring system for monitoring delay of critical path timing margins can include a plurality of adaptive monitoring circuits, where each adaptive monitoring circuit is coupled to a corresponding one of a plurality of paths in a circuit. Each adaptive monitoring circuit can include a first delay element designed to cause a mean timing margin of the plurality of N paths in the circuit to be within one minimum mean unit delay; a second delay element coupled to the first delay element and designed to add a mean delay of k*&#x3c3;; a set-up capture element capturing an output of the second delay element; and a set-up warning comparison element that outputs a set-up warning signal when the output of the set-up capture element and a shadow capture element or a capture element of the corresponding one of the plurality of paths do not satisfy an expected condition.

Delay monitoring scheme for critical path timing margin

The present techniques disclose a logic gate for an adaptive voltage scaling monitor, the logic gate comprising an inverting output and further comprising an imbalance between the drive strength of an NMOS component and a PMOS component thereof, and wherein the imbalance is operable to cause a switching delay of the gate to be primarily dependent on one of the NMOS component or the PMOS component.

Adaptive voltage scaling methods and systems therefor

Various implementations described herein refer to an integrated circuit having a row of bitcells that are chained together in series to operate as a ring oscillator. Each bitcell in the row of bitcells has multiple transistors that are independent of additional transistors to form the ring oscillator. The multiple transistors of each bitcell in the row of bitcells are arranged to function as an inverter.

Ring oscillator based bitcell delay monitor

Various implementations described herein are directed to an integrated circuit with logic circuitry having one or more components. The integrated circuit may include performance sensing circuitry that provides a performance sensing output associated with detecting variation of switching delays of the one or more components forming the logic circuitry. The integrated circuit may include transient sensing circuitry that receives the performance sensing output and provides a transient sensing output for determining stability of operating conditions of the performance sensing circuitry during one or more sampling periods. The transient sensing circuitry may use a finite state machine (FSM) to sense and classify changes in temporal behavior of the transient sensing output.

Transient sensing circuitry

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry connected between a high voltage source and a low voltage source. The core circuitry may include multiple transistors including a first transistor of a first polarity type and a second transistor of a second polarity type that is different than the first polarity type. The integrated circuit may include voltage regulation circuitry connected between an external positive voltage source and ground. The voltage regulation circuitry may operate to provide the low voltage source to the core circuitry. The low voltage source may be equal to or higher than ground. The voltage regulation circuitry may further operate to body bias the multiple transistors with a single voltage that is applied to a body terminal of the first transistor and the second transistor.

Configuration of voltage regulation circuitry

Methods and devices are described, including a near-field communications (NFC) or radio frequency identification (RFID) device comprising an NFC or RFID circuit, an antenna having at least a first terminal, a first rectifier connected to the first terminal of the antenna, a switch between the first rectifier and the NFC or RFID circuit, a voltage detector for detecting a voltage in the device caused by a signal received at the antenna, and a control module for controlling the switch, wherein when the voltage exceeds a threshold magnitude, the control module controls the switch to be in an open state and, after a predetermined time period, determines whether the voltage still exceeds the threshold magnitude and, if the voltage still exceeds the predetermined magnitude, controls the switch to be in the open state.

Protection of an NFC or RFID radio in the presence of strong electromagnetic fields

A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer that forms base cells within a plurality of logic standard cells in a CMOS process technology that includes conventional symmetric CMOS transistors having different threshold voltages. The asymmetrically doped CMOS transistors have a gate length exceeding 1.5 times the minimum gate length of the symmetric CMOS transistors. Regions defined by electrical junctions directly adjacent to the gate of the asymmetric transistors are formed by an implant mask exposing an area of the wafer on the source side of the transistor to receive the junction implant of the symmetric CMOS transistors with a higher threshold voltage while shielding the drain area, and a further implant mask exposing an area of the wafer on the drain side of the transistor to receive the junction implant of the symmetric CMOS transistors with a lower threshold voltage while shielding the source area.

Integral fabrication of asymmetric CMOS transistors for autonomous wireless state radios and sensor/actuator nodes

A non-volatile memory cell that includes a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor configured in parallel with the gate of the sense transistor. The coupling capacitor, sense transistor and tunnelling capacitor share a common floating gate electrode and the sense transistor includes source and drain regions arranged such that the tunnelling capacitor is defined by an overlap between the floating gate electrode and the drain region of the sense transistor. Word-line contacts may be to a separate active area from the coupling capacitor. This and/or other features can help to reduce Frenkel-Poole conduction.

Growing community of inventors

Cambridge, United Kingdom

Rainer Herberholz