Siemens Aktiengesellschaft

Infineon Technologies Ag

Rainer H&ouml;hler

Gunnar H Krause

Mathias Von Borcke

The circuit has a clock input for supplying a first clock signal and a clock generator for generating a second clock signal, said clock generator being phase-locked with respect to the first clock signal. The clock output of the clock generator is connected to a control input of a data transmission unit used for outputting data from the circuit and/or for reading into the circuit essentially in synchronism with the first clock signal. The clock generator has at least two control loops connected in succession which are used for controlling the phase angle of the second clock signal, the first control loop being used to generate from the first clock signal at least two intermediate clock signals, each of which has a particular phase angle with respect to the first clock signal, and the second control loop being used to generate the second clock signal from the intermediate clock signals. The first control loop is deactivated during the transmission of data by the data transmission unit, so that the control of the phase angle of the intermediate clock signals is interrupted.

Selectively deactivating a first control loop in a dual control loop circuit during data transmission

The invention relates to a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock. A control signal for rapidly adjusting the DLL circuit is converted into a delayed control signal, which is kept constant with the rising edge of a counter clock signal. This prevents instabilities of the counter value from occurring.

Growing community of inventors

München, Germany

Rainer Höhler

Growing community of inventors

München, Germany

Rainer H&ouml;hler

Rainer Höhler