Infineon Technologies Ag

Rainer Goettfert

Berndt Gammel

Gerd Dirscherl

Stefan Rueping

Thomas Kuenemund

Bernd Meyer

Jan Otterstedt

Oliver Kniffler

Steffen Sonnekalb

Markus Gail

Michael Goessel

Wieland Fischer

Jean-Pierre Seifert

Astrid Elbe

Erwin Hess

Dietmar Scheiblhofer

Kalman Cinkler

An integrated circuit includes a receiver configured to receive a message word and an integrated hardware decoding circuit. The decoding circuit includes a calculation unit to calculate a syndrome of the message word according to a predetermined BCH code, a logarithmization unit to establish a logarithm of each of one or more syndrome components, an arithmetic circuit to establish a logarithm of each of one or more zeros of the error locator polynomial of the BCH code on the basis of the logarithms of the syndrome components, and a bit inverter circuit to invert the one or more bits of the message word, the positions of which are specified by the logarithms of the zeros of the error locator polynomial. The integrated circuit further includes a data processing circuit to process further the message word processed by the bit inverter circuit.

Integrated circuit and method for processing an encoded message word

A device for generating a random number is suggested, the device comprising at least two shift registers, a transformation function that generates the random number based on at least one cell of each of the at least two shift registers.

Generating of random numbers

A data processing device includes a Physical Unclonable Function value source which is set up to provide a reference Physical Unclonable Function value and a plurality of subsequent Physical Unclonable Function values, the reference Physical Unclonable Function value and each subsequent Physical Unclonable Function value having a multiplicity of binary components, a determination device which is set up to determine a set of components, the value of which is identical in the plurality of subsequent Physical Unclonable Function values, and a Physical Unclonable Function reconstruction device which is set up to reconstruct the reference Physical Unclonable Function value from the subsequent Physical Unclonable Function values assuming that the values of the determined components in the subsequent Physical Unclonable Function value match the values of the determined components in the reference Physical Unclonable Function value.

Data processing devices and methods for reconstructing a PUF value

A method for determining an error vector for a data word according to a Reed-Muller Code includes determining the syndrome of the error vector according to the Reed-Muller Code, expanding the syndrome with zeroes to 1 bit length less than the length of the Reed-Muller Code, determining a code word of a Simplex Code of 1 bit length less than the length of the Reed-Muller Code whose difference to the expanded syndrome has a weight below a first threshold or equal to or above a second threshold, expanding the difference between the determined code word and the expanded syndrome by a zero, and outputting the expanded difference as error vector if its weight is below the first threshold or outputting the inverted expanded difference as error vector if the weight of the expanded difference is equal to or above the second threshold.

Method and decoder for determining an error vector for a data word according to a Reed-Muller code

In various embodiments, a method for determining an error vector in a data word is provided. The method includes determining the syndrome of the error vector, successively generating code words by cyclically interchanging one or more predefined code words, forming, for each code word generated, the sum of the syndrome supplemented with zeros to the data word length and the code word, and checking, for the code word, whether the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words, and determining the error vector as the sum of the syndrome and the code word for which the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words.

Method and data processing device for determining an error vector in a data word

A decoder includes a feedback shift register having a plurality of register elements that implement a simplex code and take a register vector for determining an appropriate syndrome fed into the feedback shift register and stored in the plurality of register elements. A combination device algebraically combines a subset of the register elements and provides a combination result vector. A majority decision-making unit ascertains a most frequently occurring value within the combination result vector and provides it as a decision result. An input selector connects an input of the feedback shift register to an input interface arrangement or to an output of the majority decision-making unit, and provides an input vector by the input interface arrangement and corresponds to the ascertained form of the physical unclonable properties as a register vector and, and provides a decision vector comprising the decision result and further decision results as a register vector.

Decoder and method for physically unclonable functions using threshold decoding

A method for reconstructing a first vector from a second vector includes: storing code for the row vectors according to a first code and a second code; correcting the row vectors of the second vector corresponding to the first vector so that the row vectors of the second vector have the same code as the row vectors of the first vector; calculating the code of the column vectors of the second vector according to the second code; comparing the code of the row vectors of the second vector with the code of the column vectors of the first vector; identifying the columns in which the first vector is unequal to the second vector; the rows in which the first vector is unequal to the second vector; and the components in which the first vector is not equal to the second vector, and correcting the components of the second vector.

Method and data processing device for reconstructing a vector

A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory.

Data processing arrangement and method for data processing

A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF Aand performing a preliminary correction of the potentially erroneous PUF Aby means of a stored correction vector Delta, to obtain a preliminarily corrected PUF B. The PUF A is reconstructed from the preliminarily corrected PUF Bby means of an error correction algorithm. A corresponding apparatus is also provided.

Apparatus and method for reconstructing a bit sequence with preliminary correction

An embodiment relates to a method for data processing that includes reading data, the data comprising overhead information and payload information, and determining a state of each portion of the data, wherein the state is one of a first binary state, a second binary state, and an undefined state. The method also includes decoding at least one portion of data that has an undefined state based on its location and based on the overhead information.

Method, apparatus and device for data processing

A random bit stream generator includes an internal state memory for storing a current internal state of the random bit stream generator and a periodic bit sequence generator configured to provide a periodic bit sequence. An output function receives a bit sequence portion of the periodic bit sequence and a first internal state portion of the current internal state. A new output bit of the random bit stream is determined, by the output function, based on a Boolean combination of the bit sequence portion and the first internal state portion. A feedback arrangement feeds the new output bit back to the internal state memory by performing a Boolean combination involving the new output bit and a second internal state portion of the current internal state to determine a next internal state of the random bit generator.

Random bit stream generator with guaranteed minimum period

A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.

Random bit stream generator with enhanced backward secrecy

An apparatus for recognizing a failure in a cryptographic unit, wherein the cryptographic unit includes a determinator for determining an input control signal and an output control signal, with the determinator being formed to determine the input control signal on the basis of an encryption of an input control signal parity of a group of input signals or an input signal of the group of input signals with an encryption number and to determine the output control signal on the basis of an encryption of an output control signal parity of a group of the output signals or an output signal of the group of output signals with the encryption number. Furthermore, the apparatus for recognizing includes an evaluator for evaluating the input control signal and the output control signal to recognize a failure of the cryptographic unit on the basis of a comparison between the input control signal and the output control signal.

Apparatus and method for recognizing a failure of a cryptographic unit

A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier.

Bit error correction for removing age related errors in a bit pattern

A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently influences the PRNG, and in the second mode the TRNG and the PRNG are connected to the output via the combinational logic.

Growing community of inventors

Putzbrunn, Germany

Rainer Goettfert