Infineon Technologies Ag

Rainer Findenig

Bernhard Greslehner-Nimmervoll

Christian Schmid

Alexander Melzer

Bernhard Greslehner-nimmervoll

Grigory Itkin

Markus Josef Lang

Francesco Lombardo

Ulrich Moeller

George Efthivoulidis

Martin Wiessflecker

A radar semiconductor chip includes a ramp signal generator configured to generate a frequency-modulated ramp signal comprising a plurality of frequency ramps of a ramp scenario; a first memory configured to store a sequencing program associated with generating the frequency-modulated ramp signal; a second memory configured to store a firmware program corresponding to a firmware opcode of the sequencing program; a sequencer configured to derive control values for a plurality of ramp parameters based on a plurality of ramp opcodes of the sequencing program, provide the control values to the ramp signal generator, and provide a start signal to start an execution of a firmware call in response to reading the firmware opcode; and a central processing unit configured to receive the start signal from the sequencer and, in response to the start signal, execute the firmware program from the second memory in parallel to the ramp scenario.

Sequencer firmware calls during radar ramp scenario

A semiconductor chip comprising at least one transmit channel and/or at least one receive channel for radar signals and also a sequencing circuit is proposed. In this case, the sequencing circuit is configured centrally to determine a sequencing scheme for time-dependent functions of the transmit channel and/or of the receive channel and to drive circuit elements of the transmit channel and/or of the receive channel in accordance with the sequencing scheme.

Semiconductor chip and device and method for driving at least one channel for a radar signal

A radar semiconductor chip includes a radar circuit component configured to generate at least part of a frequency-modulated ramp signal or process at least part of a reflected frequency-modulated ramp signal according to a control parameter; a memory configured to store a sequencing program associated with regulating the control parameter, wherein the sequencing program specifies a first data source, external to the sequencing program, that is configured to provide a first data value corresponding to the control parameter; and a decoder configured to read the sequencing program, access the first data value from the first data source specified by the sequencing program, derive a first control value for the control parameter from the first data value, and provide the first control value to the radar circuit component. The radar circuit component regulates a controlled circuit function in accordance with the control parameter based on the first control value.

Efficient programming model for real-time radar sequencing in a radar device

A radar device may include a memory to store a program associated with operating the radar device. The radar device may include a decoder to read the program from the memory, and generate a control value and a timestamp based at least in part on the program. The control value may be a value to be provided as an input to a component of the radar device at a time indicated by the timestamp. The radar device may include a first-in first-out (FIFO) buffer to store at least the control value and provide the control value as the input to the component of the radar device at the time indicated by the timestamp.

Modular sequencer for radar applications

A radio frequency (RF) circuit includes an input terminal configured to receive a reception signal from an antenna; an output terminal configured to output a digital output signal; a receive path including a mixer and an analog-to-digital converter (ADC), wherein the receive path is coupled to and between the input and output terminals, wherein the receive path includes an analog portion and a digital portion, and wherein the ADC generates a digital signal based on an analog signal received from the analog portion; a test signal generator configured to generate an analog test signal injected into the analog portion of the receive path; and a digital processor configured to receive a digital test signal from the digital portion, the digital test signal being derived from the analog test signal, analyze a frequency spectrum of the digital test signal, and determine a quality of the digital test signal.

Automatic interference detection and avoidance in radar transceiver systems

A radar system is provided that includes a radar monolithic microwave integrated circuit (MMIC). The radar MMIC includes a plurality of radar signal channels; and at least one sensor configured to measure a physical parameter related to a temperature of the radar MMIC, and to generate sensor data corresponding to measured values of the physical parameter; and a controller configured to receive the sensor data from the at least one sensor, and to determine a channel operation of the plurality of radar signal channels, including selectively disabling at least a first radar signal channel of the plurality of radar signal channels and selectively enabling at least a second radar signal channel of the plurality of radar signal channels based on the measured values.

Dynamic radar signal channel deactivation in a cascaded radar system for active temperature control

A device for monitoring a digital control unit with regard to functional safety is proposed. The device comprises an interface configured to receive a control signal of the digital control unit for a circuit component. The control signal represents a digital value. Furthermore, the device comprises a timer circuit configured to output an associated timer value in each case for successive points in time. The device furthermore comprises a hash value generator, which is configurable, in response to a change in the digital value, to recalculate a hash value on the basis of the change in the digital value and the timer value at the point in time of the change in the digital value.

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Linz, Austria

Rainer Findenig