Robert Boschgmbh

International Business Machines Corporation

Rainer Dorsch

Gerhard Lammel

Christian Haubelt

Sebastian Stieber

Markus Buehler

Thomas Schwarz

Guenther Hutzl

Dorde Cvejanovic

Cagri Balkesen

Stefanie Scherzinger

David Rohr

Michael W Kaufmann

Anna Christina Strohrmann

Daniel Pfefferkorn

Martin Eckert

Markus Helms

Thomas Schlipf

Andreas Wagner

Daniel D Sentler

Walter Heinrich Lipponer

Sergej Scheiermann

Jan Hayek

Philipp Salz

Thomas Claus

Gerhard Zilles

Timo Giesselmann

Rudolf Bichler

Marta Junginger

Harmut Ulland

Shengxian Liu

Omar Elrhoul

Matthias Scheulin

Lars Middendorf

Urs Kanus

Konstantin Buck

Guido Retz

An inertial sensor unit, including a sensor element for detecting and converting movements and vibrations into an electrical sensor signal, a signal processing element for evaluating the sensor signal, and an interface for signaling a detected speech activity. The signal processing element includes a first processing stage which checks a first criterion for the presence of a speech activity, and a second processing stage which checks a second criterion for the presence of a speech activity, the second processing stage being passed through only if the sensor signal has passed through the first processing stage and the first criterion for the presence of a speech activity has been met. The signal processing element is designed to activate the interface for signaling a speech activity only if the sensor signal has passed through the second processing stage, and the second criterion for the presence of a speech activity has been met.

Inertial sensor unit and method for detecting a speech activity

A system component having a configurable communication behavior. The system component includes at least one interface for a data bus for the communication with at least one further system component. A defined communications protocol for the transmitting and receiving of data and bus commands is used on the data bus. The communications protocol provides that the at least one further system component queries the communication behavior of the system component via the data bus to adapt its own communication behavior to that of the system component. The system component includes a register for configuration data that define the communication behavior of the system component on the data bus, the register being connected to the data bus so that the configuration data stored in the register are available on the data bus. The function scope of the system component allows for different communication behaviors.

System component having a configurable communication behavior, and method for operating such a system component

A sensor unit includes at least one sensor for detecting and converting measured quantities into sensor signals; at least one microprocessor; at least one memory for program modules for processing sensor signals, the program modules being executable on the microprocessor; and at least one communications interface to an external application processor, the program modules being able to be activated and deactivated via this communications interface, and further program modules are able to be loaded into the memory via this communications interface. The microprocessor includes at least one closed environment for executing plug-in program modules.

Processing control of a sensor system

A method for operating an event counter, including the following: ascertaining at least one counting event with the aid of a signal from a first sensor; and using a signal from a second sensor for ascertaining the counting event if the signal from the first sensor is unable to be unequivocally allocated to a counting event.

Method for operating an event counter

A method for synchronizing sensor data of a sensor system with the host time base of a host system, based on the clock ratio of the sensor time base to the host time base. To ascertain the clock ratio for at least two communication events, a time stamp acquisition is performed for each event, in which a sensor time stamp and a host time stamp is recorded. The communication events for ascertaining the clock ratio relate to a specific quantity of data. The ratio is ascertained/updated repeatedly; the duration of the individual communication events for the time stamp acquisition are measured; and by comparing each measured duration to a comparison value, possible irregularities in the communication event are detected. The host time stamp of a time stamp acquisition is corrected/replaced by a calculated host time stamp based on the measured irregularities. Also described is a related device for the method.

Method for adjusting time stamps during the acquisition of sensor data

A sensor system including a sensor data buffer, the sensor data buffer being configured in such a way that sensor data are organized in frames. The sensor data buffer is configured in such a way that a frame has a header and a sensor data area.

Sensor system with a sensor data buffer

A method is provided for detecting a double-click input on an electrical device and an electrical device, the detection of the double-click input taking place by analyzing at least one input signal generated with the aid of at least one acceleration sensor, in a first method step (or task), it being monitored whether the input signal falls below a predefined first threshold value in absolute value during a first predefined time interval, in a second method step, exceeding of a second threshold value in absolute value by the input signal is detected, in a third method step, it being monitored whether the input signal falls below a predefined third threshold value in absolute value during a third predefined time interval, and in a fourth method step, exceeding of a fourth threshold value in absolute value by the input signal being detected.

Method for detecting a double-click input

A FIFO memory having a modifiable memory region; the FIFO memory being configured as a linear memory and as a circular buffer; the FIFO memory having a state machine that contains a new base value and a new top value for definition of a memory region allocated in the future, the lower boundary of which region is defined by the new base value and the upper boundary of which is defined by the new top value, and the state machine is configured in such a way that in a read mode and/or a write mode of the FIFO memory, the allocated memory region of the FIFO memory is modifiable by shifting the base pointer to the new base value, and/or by shifting the top pointer to the new top value.

FIFO memory having a memory region modifiable during operation

A sensor for acquiring measured values and for outputting data samples having at least one first register for storing a sensor time, which includes time information on phase position and/or period of the data samples, the first register being readable out externally. The sensor includes at least one second register, which is writable on externally, and by which the phase position and/or the period of the data samples is able to be set in the sensor. Also described is a sensor system having at least one sensor and an external control unit by which at least the first register is readable and at least the second register is writable. Also described is a sensor-fused system having at least one sensor system having at least two sensors. Also described is a method for setting the phase position and/or the period of data samples in a sensor system or a sensor-fused system.

Sensor time synchronization

A sensor includes: a detection element; an analog front end; a digital back end, the digital back end being connected to a control unit via a digital interface, and the sensor providing sampled data in the digital back end; and a timer unit for providing pieces of time information of the sampled data in the digital back end which the control unit is able to access via the digital interface.

Sensor time

The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

Write buffer for improved DRAM write access patterns

First and second sets of numbers are received in an input range, which is separated into sub ranges. A first sub range is processed by initializing bits of a memory to a first logical state and by changing the initial state of each of the bits corresponding to a received number of the first set that is within the first sub range. Each number received in the second set is compared to a bit in the memory to identify a set of received numbers that are in the first sub range and that are in both the first set and the second set. The comparing is responsive to detecting a change of initial state of any bit in the memory during the processing of the first sub range. The processing and comparing is repeated for remaining sub ranges to identify received numbers that are in both the sets.

Computing intersection of sets of numbers

A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the netlist is performed, the N user logics in N macro test wrappers are instantiated resulting in N instantiated logics. After said instantiating the N user logics is performed, the N instantiated logics are processed. After said processing is performed, a result of said processing is back-annotated to the netlist.

Method for circuit design

The present invention generally relates to digital network communication, and in particular to processing data according to the InfiniBand&#x2122; (IB) Protocol with reduced latency and chip costs in an InfiniBand&#x2122; type computer system. ID information in a packet header is obtained before the body of the packet has completely arrived at a receiving Channel adapter. The ID information is used to obtain work Queue Pair Context (QPC) and when needed an associated Work Queue Element (WQE), for operating on the data content of the packet being received.

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Dettenhausen, Germany

Rainer Dorsch