Infineon Technologies Ag

Siemens Aktiengesellschaft

Infineon Ag

Kabushiki Kaisha Toshiba

Forschungszentrum Juelich Gmbh

Rheinisch-westfaelische Technische Hochschule Aachen (rwth)

Rainer Bruchhaus

Nicolas Nagel

Stefan Gernhardt

Walter Hartner

Karl Hornik

Uwe Wellhausen

Andreas Hilliger

Haoren Zhuang

Gerhard Enders

Thomas Mikolajick

Wolfram Wersing

Ulrich Egger

Robert Primig

Jingyu Lian

Jenny Lian

Matthias Kr&ouml;nke

Dana Pitzer

Michael R&ouml;hner

Martin Gutsche

G&uuml;nther Schindler

Igor Kasko

Franz Hofmann

Volker Lehmann

Wolfgang Werner

Manfred Engelhardt

Koji Yamakawa

Hermann Wendt

Lothar Risch

Heinz Hoenigschmid

Frank S Hintermaier

Hiroshi Itokawa

Volker Weinrich

Cay-Uwe Pinnow

Corvin Liaw

Carlos Mazure-Espejo

Matthias Schreiter

Joerg W Wohlfahrt

Rainer M Waser

Bum-ki Moon

Bum-Ki Moon

Matthias Krönke

Wolfgang H&ouml;nlein

Ilia Valov

Eike Linn

Roland Daniel Rosezin

Michael Röhner

Lutz Nielen

Stefan Tappertzhofen

Jing Yu Lian

Andre&aacute;s Hilliger

Florian Lentz

A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit is measured and an electrical variable is selected for this measurement, to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A instate A1 makes a different contribution than the memory cell B in state B1. The two state combinations A1 and B0 or A0 and B1 then result in differing values for the electrical variable that is measured by way of the series circuit. These state combinations can thus be distinguished from each other without having to change the logic state of the memory element during reading.

Method for nondestructively reading resistive memory elements

The present invention is related to a memory circuit comprising: a resistive memory element comprising a programmable metallization cell, a bit line, a selection transistor operable to address the resistive memory element for coupling the resistive memory element to the bit line, and a further transistor coupled with the resistive memory element for applying a predefined potential at a node between the selection transistor and the resistive memory element.

Memory circuit, method for operating a memory circuit, memory device and method for producing a memory device

A semiconductor device according to the present invention comprises a semiconductor substrate, a capacitor including a lower electrode disposed above the semiconductor substrate, a dielectric film disposed above the lower electrode, and an upper electrode disposed above the dielectric film, the upper electrode including metal oxide formed of ABOperovskite oxide and containing at least an Ru element as a B site element, and a metal film containing a Ti element being disposed between the dielectric film and the upper electrode.

Semiconductor device and method of manufacturing the same

An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.

Self-aligned V0-contact for cell size reduction

The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (), in which method a shaping layer () is provided and is patterned in such a manner that vertical trench structures () are formed perpendicular to the surface of the driving unit (). Deposition of a seed layer () on side walls () of the trench structures () allows a crystallization agent () which has filled the trench structures (), during crystallization, to have grain boundaries perpendicular to electrode surfaces that are to be formed. This provides memory cells based on vertical ferroelectric capacitors in a chain FeRAM structure.

Method for fabricating memory cells for a memory device

A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.

Ferroelectric memory arrangement

Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the AlOlayer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.

Method for forming ferrocapacitors and FeRAM devices

In a process for fabricating a ferrocapacitor comprising providing ferroelectric PZT elements over an AlOlayer, the AlOlayer is covered with a seed layer comprising layers of PZT and TiO. Then a thicker layer of PZT is formed over the seed layer and crystallized. By this process, the crystallinity of the thick PZT layer is much improved, and its orientation is improved to be in the (111) direction. Furthermore, the seed layer reduces downward diffraction of Pb from the thick PZT layer, such as through the AlOinto a TEOS structure beneath.

Process for fabrication of a ferrocapacitor

A process for the fabrication of a ferroelectric capacitor comprising depositing a layer of Tiover an insulating layerof AlO, and oxidising the Ti layer to form a TiOlayerSubsequently, a layer of PZTis formed over the TiOlayerThe PZT layeris subjected to an annealing step in which, due to the presence of the TiOlayerit crystallises to form a layerwith a high degree of (111)-texture.

Process for fabrication of a ferroelectric capacitor

A process for fabricating a ferrocapacitor comprises etching a layer of amorphous PZT formed over a layer having a low concentration of nucleation centres for PZT crystallisatlon. The etching step forms individual PZT elements. The side surfaces of the PZT elements are then coated with a layer of a material which promotes crystallisation of the PZT, such as one having a high concentration of PZT crystallisation centres (e.g. TiO), and a PZT annealing step is carried out. The result is that the PZT has a high degree of crystallisation, with grain boundaries extending substantially horizontally through the PZT elements.

A method of etching a ferroelectric devicehaving a ferroelectric layerbetween a top and a bottom electrodeis disclosed herein. Hardmasksare deposited on the top electrode, two or more hardmasks being spaced apart by narrow first regionsand spaced apart from other hardmasks by wider second regions. The top electrodeand ferroelectric layerare then etched to pattern the top electrodethus forming capacitors, and the bottom electrodeis etched by a process in which the second regions are etched more slowly than the second regions. Those capacitors having a first region between them have a common bottom electrode, but in the second regions the bottom electrode is severed. To pattern the bottom electrode, a fluorine-based chemistry followed thereafter by a CO-based chemistry are used in a two step etching process.

Method of etching ferroelectric devices

An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.

A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or more contact plugs through the substrate. A conducting layer is formed on the first interlayer dielectric layer and an electrode is formed on alternate ones of the contact plugs by etching the conducting layer. The etched electrodes are then coated with a ferroelectric layer. The ferroelectric layer is etched from the surfaces separating the contact plugs and additional electrodes are created by filling the spaces between the electrodes on alternate ones of the contact plugs with a conductive material to establish electrical contact between the plugs and the electrodes.

Device and a method for forming a capacitor device

The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.

Side-wall barrier structure and method of fabrication

Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.

Radiation protection in integrated circuits

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Munich, Germany

Rainer Bruchhaus