Nokia Mobile Phones Limited

Raimo K Kivari

Seppo Eerik Salow

Mikko Lietsalmi

Jaakko S Vanttila

Timo Kolehmainen

Arto Pussinen

Juha Vaihoja

Jorma Seppanen

Juha Pikkarainen

Veijo L Kontas

Pertti J Korhonen

Juha H Tenhunen

Seppo Salonen

Esko K Strommer

The data decoding logic arrangement of the invention provides 3/5 voting on data blocks received (1) in a frame. The decoded data (12) is preferably clocked out during reception of the first data block of the next frame, in synchronism with the clock frequency (2) generated from the received data bit flow. The inventive procedure is used on FOCC and FVC channels in the TACS/AMPS mobile phone system.

Data decoding logic in a mobile phone

A method is disclosed for operating a cellular telephone that includes a first step, executed in response to input from a user, of disabling the cellular telephone from receiving cellular telephone calls. A second step then periodically enables the cellular telephone to receive, store and display user-related messages from a network control channel. In one embodiment the step of disabling includes a step of de-registering the cellular telephone from the network, and the step of periodically enabling includes an initial step of re-registering the cellular telephone with the network. The step of disabling may include a step of reducing the power consumption of the cellular telephone. In accordance with a further aspect of this invention the step of periodically enabling includes an initial step of requesting the network to assign the cellular telephone to a predetermined paging frame class that insures that the cellular telephone will receive a paging message from the network every n seconds. The step of periodically enabling thus further includes the step of placing the cellular telephone in a low power mode of operation for n-x seconds, where x is a period of time at least equal to a time required to resynchronize the cellular telephone to the network control channel.

Mobile terminal having user-actuated pager mode

A cellular telecommunications system includes at least one base station and at least one user terminal that is bidirectionally coupled to the at least one base station through an RF interface. The system further includes system circuitry for composing messages and transmitting composed messages continuously over a forward RF link to the at least one user terminal. The messages include filler messages and other messages, and the circuitry composes the messages for specifying in a transmitted message a number of filler messages that will be consecutively transmitted. The user terminal includes a receiver for receiving messages from the forward RF link and circuitry for determining a number of consecutive filler messages that will be transmitted. The user terminal further includes a controller that is responsive to a received message for placing the user terminal in a powered-down state for a period of time that is a function of the number of consecutive filler messages. In a preferred embodiment of this invention the message is repeated a plurality of times during a message frame, and the user terminal receives at least one repeat of the message. Also in a preferred embodiment of this invention, the message employs bits that are specified as reserved bits for transmitting the number of filler messages, thus making the teaching of this invention downwards compatible with existing cellular telecommunications systems, such as that specified by EIA/TIA-553 and similar systems.

Mobile terminal having power saving mode that monitors specified numbers

A method and system for operating a radiotelephone at reduced power provides for a deenergization of a receiver of the radiotelephone wherein the receiver, during periods of activation, receives a sequence of messages of a control channel, each message having a synchronization portion and a data portion which follows the synchronization portion. Included within the radiotelephone is signal processing circuitry synchronized by a synchronization portion of an individual one of the messages to permit a reading of data of the data portion of an individual one of the messages. A digital phase locked lop (DPLL) with phase adjustment capability enables operation of synchronization circuitry and the data reading circuitry. Electronic circuitry within the DPLL provides for inhibiting the phase adjustment function in response to the command of a controller of the radiotelephone subsequent to a reading of data and concurrently with a termination of power to the receiver. The phase adjustment function is enabled upon reactivation of the receiver and operation of the data reading circuitry for reading data of a subsequent message.

Operation of a radiotelephone in a synchronous extended standby mode for

This invention provides a method, and apparatus for performing the method, for reducing the power consumption of a radiotelephone. The method includes the steps of (a) receiving with a receiver of a radiotelephone at least a Word Synchronization pattern from a frame that is transmitted over a control channel; (b) receiving a first repeat of a control message that follows the Word Synchronization pattern within the frame; and (c) determining if the first repeat was correctly received. If the first repeat was correctly received, the method includes a further step of (d) determining if at least one reception-related criteria is met. If the reception-related criteria is determined to be met, the method includes a further step of (e) selectively removing operating power from one or more portions of the radiotelephone receiver for a predetermined time period during a remainder of the frame. The at least one reception-related criteria is a Message Error Rate (MER) that indicates a number of correctly received frames out of a total number of n last received frames. The reception-related criteria may also include a difference between a minimum Received Signal Strength Indicator (RSSI) value and a maximum RSSI value that are detected during a predetermined interval of time.

Method and apparatus for operating a radiotelephone in an extended

The inventive data decoding system provides 3/5 voting on data blocks (1 . . . 11) received in a frame. A counter circuit of the system counts the bits in the data blocks and raises a repeat flag (RFLAG) at the end of each data block. The RFLAG signal causes an interrupt in a controlling processor, enabling the processor to monitor and control the receiving synchronism. The inventive procedure can be used on Forward Control Channel (FOCC) and Forward Voice Channel (FVC) channels in the Total Access Communication System (TACS) or the Advanced Mobile Phone Services (AMPS) mobile phone systems.

Indication of data blocks in a frame received by a mobile phone

Apparatus operable with different cellular telephone systems and signalling protocols is described. Signalling messages, both data messages and supervisory related signals between a cellular telephone microcontroller (4) and a base station are transferred via a baseband signalling circuit (10). The baseband signalling circuit is operable to employ different signalling protocols, the protocol being selected by control bits provided from the microcontroller to the signalling circuit. In a preferred embodiment, the signalling protocol selection is made between an AMPS/TACS signalling protocol and a NAMPS/NTACS subaudible signalling protocol.

Cellular telephone signalling circuit operable with different cellular

A signal generator includes a frequency divider having an input node for receiving a first signal having a first frequency f.sub.1 and a single output node for outputting a second signal having a second frequency f.sub.2, wherein a ratio f.sub.1 /f.sub.2 is equal to an odd number that is equal to or greater than three. A synchronous delay circuit has an input node coupled to the single output node of the frequency divider and an output node for outputting a third signal that is delayed in time with respect to the second signal by an amount that is a function of a period of the first signal. Logic is provided having a first input node coupled to the single output node of the frequency divider and a second input node coupled to the output node of the delay circuit. The logic has an output node for outputting a fourth signal having the second frequency f.sub.2 and a 50% duty cycle. In a further embodiment the signal generator outputs a frequency that is (2n+1)/2 of the input frequency, where n any positive integer.

Circuit arrangement

A circuit arrangement for a mobile telephone comprises a microprocessor responsive to a clock signal for controlling its functions, and a signalling circuit, e.g. a modem which is coupled to the microprocessor to provide an output clock signal thereto. In the idle states of the processor, the output clock signal is stopped, using a stop signal from the microprocessor. This gives use to reduce power consumption and a consequential increase in battery life.

Mobile telephone having a power-conserving subroutine

A receiver synchronization control in signalling messages in TACS/AMPS system in a mobile phone is disclosed. In order to avoid unnecessary setting of hunt mode operation, if the received synchronization pattern is not congruent with the correct reference pattern, the received pattern is checked in a bit-by-bit manner so as to reveal occasional bit errors of one or two bits, which may appear although the receiver is in synchronization. A further check may be conducted by shifting a reference pattern mask by one or at the most two bits in either direction, whereafter rechecking to reveal either fully correct pattern or rechecking for only one or two bits error can be performed.

Method for the control of receiver synchronization in a mobile phone

A frequency detection system is based on a digital phase locked loop, the detection system being especially suitable for use in noisy environments like supervisory audio tone (SAT) detection in AMPS and TACS mobile telephone systems. In addition to the digital phase locked loop (4), the frequency detection system according to the invention incorporates a detector circuit (5), which comprises a detection timer (6) and two phase detectors VI1 (7) and VI2 (8). The timer (6) forms a detection sequence of desired length, at the end of which the output signal (SATVAL) of the detector circuit is updated. The first phase detector VII (7) has a phase window in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with the window. The second phase detector VI2 (8) also has a phase window of its own in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with its window. The phase windows are made up of the basic output signal of the digital phase locked loop (SO1) and its 2nd, 4th, and 8th harmonics (SO2, SO4 and SO8). If at the end of a detection sequence the counter of the first phase detector VII (7) exceeds, and the counter of the second phase detector VI2 (8) falls short of their predetermined threshold values, the detection circuitry (5) will indicate that the frequency of the received signal is correct.

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Haukipudas, Finland

Raimo K Kivari