Texas Instruments Corporation

Intel Corporation

Juniper Networks, Inc.

Rahul Vijay Kulkarni

Shridhar Atmaram More

Kaustubh Ulhas Gadgil

Abhishek R Appu

Joydeep Ray

Vasanth Ranganathan

Ben J Ashbaugh

Jeffery S Boles

James A Valerio

Srinivasan Embar Raghukrishnan

Amal Kumar Kundu

Brandon L Fliflet

Minkle Eldho Paul

Rathi Kartheek

Abhijeet Gopal Godbole

Sharat Chandra Rudrasamudram

Kaustubh Gadgil

Siva Reddy Vemireddy

An analog to digital (A/D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S/H) output. The A/D converter also includes a voltage comparator having a first input coupled to the S/H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage. The A/D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.

Analog to digital (A/D) converter with internal diagnostic circuit

An integrated self-test mechanism for monitoring an analog-to-digital converter (ADC), a reference voltage (V) source associated with the ADC, a low-dropout regulator (LDO), or a power supply is provided. In one example, an ADC that is associated with an integrated circuit (IC) can monitor its own V, the voltage (V) of an LDO associated with the IC, or the voltage (AVDD) provided to an electrical coupling mechanism in the IC that is coupled to a power supply associated with the IC. The ADC can generate a digital output code based, at least in part, on the Vand one or more of the Vand the AVDD. The digital output code can be used to determine whether one or more of the ADC, the Vsource, the LDO, and the power supply is malfunctioning or nonoperational.

Integrated self-test mechanism for an analog-to-digital converter, a reference voltage source, a low dropout regulator, or a power supply

A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.

Sample and hold circuit with indefinite holding time

A method for testing an A/D converter with a built-in diagnostic circuit with a user supplied variable input voltage includes generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code. The method further includes applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage. The method also includes applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage. The method also includes determining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits.

Systems and methods for testing analog to digital (A/D) converter with built-in diagnostic circuit with user supplied variable input voltage

Disclosed examples include a method and automated test system for testing an ADC. The method includes computing an ADC noise value based on a first set of data values sampled while the ADC input terminals are shorted, computing a first system noise value based on a second set of data values sampled while a test circuit signal source applies zero volts to the ADC through a signal chain, computing a signal chain noise value based on the first system noise value and the ADC noise value, computing a measured SNR value based on a third set of data values sampled while the test circuit signal source applies a non-zero source voltage signal to the signal chain, computing a second system noise value based on the measured SNR value, and computing an ADC SNR value based on the second system noise value and the signal chain noise value.

Low noise and low distortion test method and system for analog-to-digital converters

Embodiments described herein provide an apparatus comprising a processor to configure a plurality of contexts of a command engine to execute a graphics workload comprising a plurality of walkers, allocate, from a pool of execution units of a graphics processor, a subset of execution units to each walker in the plurality of walkers based at least in part on the predetermined number of walkers configured for the context, for each context in the plurality of contexts, dispatch one or more walkers of the plurality of walkers to the execution units, and upon dispatch of the one or more walkers of the plurality of walkers, write an opcode to a computer-readable memory indicating that the dispatch of the walker is complete, wherein the opcode comprises dependency data for the one or more walkers of the plurality of walkers. Other embodiments may be described and claimed.

System and method to support multiple walkers per command

An analog-to-digital converter includes an input terminal, a digital-to-analog converter, a comparator, and successive approximation circuitry. The input terminal is configured to receive a multi-bit digital threshold value from circuitry external to the analog-to-digital converter. The successive approximation circuitry is coupled to the comparator and the digital-to-analog converter. The successive approximation circuitry is configured to operate in a comparison mode and a conversion mode, and to provide the multi-bit digital threshold value to the digital-to-analog converter while operating in the comparison mode. The comparator is coupled to the digital-to-analog converter and the successive approximation circuitry. The comparator is configured to output a signal that indicates whether an analog input signal exceeds an analog threshold signal corresponding to the multi-bit digital threshold value.

Analog-to-digital converter

A computer-implemented method for detecting fault conditions experienced by remote physical ports may include (1) identifying a network connection between a first physical port operating in a first communication mode and a second physical port operating in a second communication mode, (2) monitoring at least one count that identifies the number of block-sized transmission errors encountered by the first physical port, (3) determining that the second physical port has experienced a fault condition based at least in part on the count that identifies the number of block-sized transmission errors encountered by the first physical port and then, in response to determining that the second physical port has experienced the fault condition, (4) deactivating the network connection to avoid dropping network traffic directed to the network connection. Various other systems, methods, and apparatuses are also disclosed.

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Bengaluru, India

Rahul Vijay Kulkarni