Intel Corporation

Rahul Shukla

Jay S Heeb

Timothy J Jehl

A method and apparatus for hit-dependent flushing of cacheable memory access operations in a bus controller queue is described. The present invention is implemented in the context of a computer system including a microprocessor coupled to an external memory device through an external bus. The processor includes a processor core for issuing memory access operations, a cache, and a bus controller. The bus controller includes a queue having slots for storing pending memory access operations to be sent out over the external bus. After a first memory access operation is issued, the bus controller stores the first memory access operation in a first queue slot before it is determined whether the first operation hits or misses the cache. The bus controller flushes the first operation from the queue if the first operation hits the cache. In response to the processor core issuing a second memory access operation, the bus controller stores the second memory access operation in the first queue slot if the first operation hits the cache. If, on the other hand, the first operation misses the cache, then the bus controller stores the second memory access operation in a second queue slot. Preferably, the first operation is issued in a first cycle and stored in the first queue slot in a second cycle that immediately follows the first cycle, and the second operation is issued in the second cycle.

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Tempe, AZ, United States of America

Rahul Shukla