Sandisk Technologies Inc.

Nanosys, Inc.

Mattson Thermal Products Gmbh

Rahul Sharangpani

Raghuveer S Makala

Fei Zhou

Adarsh Rajashekhar

Senaka Kanakamedala

George Matamis

Sateesh Koka

Yanli Zhang

Yao-Sheng Lee

Somesh Peri

Seung-Yeul Yang

Johann Alsmeier

Keerti Shukla

Naoki Takeguchi

Fumitaka Amano

Monica Titus

Roshan Jayakhar Tirukkonda

Wei Zhao

Bhagwati Prasad

Ramy Nashed Bassely Said

Srikanth Ranganathan

Genta Mizuno

Masaaki Higashitani

James K Kai

Masanori Tsutsumi

Kensuke Yamaguchi

Yusuke Mukae

Kartik Sondhi

Christopher John Petti

Tatsuya Hinoue

Akio Nishida

Thomas Jongwan Kwon

Zhenyu Lu

Tomoyuki Obu

Tiffany Santos

Yujin Terasawa

Joyeeta Nag

Toshihiro Iizuka

Tomohiro Uno

Mark Juanitas

Yingda Dong

Hiroyuki Ogawa

Peter Rabkin

Jayavel Pachamuthu

Tuan Duc Pham

Ching-Huang Lu

Hiroyuki Kinoshita

Henry Chien

Jian Chen

Kiyohiko Sakakibara

Seiji Shimabukuro

Peng Zhang

Yangyin Chen

Shigehisa Inoue

Atsushi Suyama

Tomohiro Kubo

Matthias Baenninger

Lin Hou

Junichi Ariyoshi

Shigehiro Fujino

Marika Gunji-Yoneoka

Yusuke Ikawa

Sing-Pin Tay

Eisuke Takii

Motoki Kawasaki

Bing Zhou

Yuichi Ikezono

Xiaofeng Liang

A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a first etch mask material layer, forming a first cladding liner, and forming a via opening through the alternating stack by performing an anisotropic etch process that employs a combination of at least the first cladding liner and the first etch mask material layer as a composite etch mask structure.

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a metallic barrier liner containing an intermetallic compound of at least two elements that includes a first metal element including Ta or Ti, and a second metal element including at least one of Al or Mo, and metallic barrier liner containing less than 10 atomic percent of nitrogen and oxygen, and a metallic fill material layer contacting the metallic barrier liner.

Three-dimensional memory device with intermetallic barrier liner and methods for forming the same

A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Memory device containing composition-controlled ferroelectric memory elements and method of making the same

A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.

Bonded assembly including interconnect-level bonding pads and methods of forming the same

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a first backside trench fill structure and a second backside trench fill structure. Each of the electrically conductive layers includes a respective metal nitride liner and a respective metal fill material region. The respective metal fill material region includes a respective first-thickness portion having a respective first vertical thickness and a respective second-thickness portion having a respective second vertical thickness that is greater than the respective first vertical thickness.

Three-dimensional memory device containing variable thickness word lines with reduced length metal nitride diffusion barriers and methods for forming the same

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film. The memory film includes a contoured blocking dielectric layer including sac-shaped lateral protrusions located at levels of the electrically conductive layers, a tunneling dielectric layer in contact with the vertical semiconductor channel, and a vertical stack of charge storage material portions located within volumes enclosed by the sac-shaped lateral protrusions.

Three-dimensional memory device including discrete charge storage elements and methods of forming the same

A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask.

A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

Methods and apparatuses for forming semiconductor devices containing tungsten layers using a tungsten growth suppressant

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

Three-dimensional memory device with vertical word line barrier and methods for forming the same

A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

Semiconductor device containing bit lines separated by air gaps and methods for forming the same

A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second metallic material portion including a second metal. A metal-semiconductor alloy portion including a first metal-semiconductor alloy of the first metal and a semiconductor material is located underneath the second metallic material portion, and contacts a top surface of the first metal interconnect structure.

High aspect ratio via fill process employing selective metal deposition and structures formed by the same

A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and a vertical stack of discrete memory material portions laterally surrounding the vertical word line.

Three-dimensional NOR array including vertical word lines and discrete memory elements and methods of manufacture

Growing community of inventors

Fremont, CA, United States of America

Rahul Sharangpani