Sandisk Technologies Inc.

Nanosys, Inc.

Mattson Thermal Products Gmbh

Rahul Sharangpani

Raghuveer S Makala

Fei Zhou

Adarsh Rajashekhar

Senaka Kanakamedala

George Matamis

Sateesh Koka

Yanli Zhang

Yao-Sheng Lee

Somesh Peri

Seung-Yeul Yang

Johann Alsmeier

Fumitaka Amano

Keerti Shukla

Roshan Jayakhar Tirukkonda

Naoki Takeguchi

Monica Titus

Kartik Sondhi

Wei Zhao

Bhagwati Prasad

Ramy Nashed Bassely Said

Srikanth Ranganathan

Genta Mizuno

Masaaki Higashitani

James K Kai

Masanori Tsutsumi

Kensuke Yamaguchi

Yusuke Mukae

Christopher John Petti

Tatsuya Hinoue

Akio Nishida

Thomas Jongwan Kwon

Zhenyu Lu

Tomoyuki Obu

Tiffany Santos

Yujin Terasawa

Joyeeta Nag

Tomohiro Uno

Toshihiro Iizuka

Bing Zhou

Mark Juanitas

Yingda Dong

Hiroyuki Ogawa

Peter Rabkin

Jayavel Pachamuthu

Tuan Duc Pham

Ching-Huang Lu

Hiroyuki Kinoshita

Henry Chien

Jian Chen

Peng Zhang

Kiyohiko Sakakibara

Seiji Shimabukuro

Yangyin Chen

Atsushi Suyama

Shigehisa Inoue

Tomohiro Kubo

Matthias Baenninger

Lin Hou

Junichi Ariyoshi

Shigehiro Fujino

Marika Gunji-Yoneoka

Yusuke Ikawa

Sing-Pin Tay

Eisuke Takii

Motoki Kawasaki

Kensuke Ishikawa

Ryo Kambayashi

Shingo Totani

Yuichi Ikezono

Xiaofeng Liang

Kyohiko Sakakibara

Senaka Krishna Kanakamedala

A method of forming a memory device includes forming an alternating stack of insulating layers including a first insulating material and sacrificial material layers including a first sacrificial material over a substrate, forming a memory opening through the alternating stack, performing a first selective material deposition process that selectively grows a second sacrificial material from physically exposed surfaces of the sacrificial material layers to form a vertical stack of sacrificial material portions; forming a memory opening fill structure in the memory opening, where the memory opening fill structure includes a vertical stack of memory elements and a vertical semiconductor channel, and replacing a combination of the vertical stack of sacrificial material portions and the sacrificial material layers with electrically conductive layers.

Three-dimensional memory device and method of making thereof by non-conformal selective deposition of insulating spacers in a memory opening

A three dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory stack structures vertically extending through the alternating stack; and a backside trench fill structure. The backside trench fill structure includes a backside trench insulating spacer and a backside contact via structure. The backside contact via structure may include a tapered metallic nitride liner and at least one core fill conductive material portion. Alternatively, the backside contact via structure may include a tungsten nitride liner, a metallic nitride liner other than tungsten nitride, and at least one core fill conductive material portion.

Three-dimensional memory device including composite backside metal fill structures and methods for forming the same

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer, a continuous charge storage material layer vertically extending through a plurality of the electrically conductive layers, a vertical stack of discrete charge storage elements located at levels of the electrically conductive layers and contacting a respective surface segment of an outer sidewall of the continuous charge storage material layer, and a vertical stack of discrete blocking dielectric material portions containing silicon atoms and oxygen atoms and located at the levels of the electrically conductive layers and vertically spaced apart from each other.

Three-dimensional memory device containing engineered charge storage elements and methods for forming the same

A bonded assembly includes a first semiconductor die that includes first metallic bonding structures embedded within a first bonding-level dielectric layer, and a second semiconductor die that includes second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding. One of the first metallic bonding structures a pad portion, and a via portion located between the pad portion and a first semiconductor device in the first semiconductor die, the via portion having second tapered sidewalls.

Bonded assembly including interconnect-level bonding pads and methods of forming the same

A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a memory material layer having a straight inner cylindrical sidewall that vertically extends through a plurality of electrically conductive layers within the alternating stack without lateral undulation and a laterally-undulating outer sidewall having outward lateral protrusions at levels of the plurality of electrically conductive layers.

Three-dimensional memory device including discrete charge storage elements and methods of forming the same

A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a first etch mask material layer, forming a first cladding liner, and forming a via opening through the alternating stack by performing an anisotropic etch process that employs a combination of at least the first cladding liner and the first etch mask material layer as a composite etch mask structure.

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a metallic barrier liner containing an intermetallic compound of at least two elements that includes a first metal element including Ta or Ti, and a second metal element including at least one of Al or Mo, and metallic barrier liner containing less than 10 atomic percent of nitrogen and oxygen, and a metallic fill material layer contacting the metallic barrier liner.

Three-dimensional memory device with intermetallic barrier liner and methods for forming the same

A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Memory device containing composition-controlled ferroelectric memory elements and method of making the same

A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a first backside trench fill structure and a second backside trench fill structure. Each of the electrically conductive layers includes a respective metal nitride liner and a respective metal fill material region. The respective metal fill material region includes a respective first-thickness portion having a respective first vertical thickness and a respective second-thickness portion having a respective second vertical thickness that is greater than the respective first vertical thickness.

Three-dimensional memory device containing variable thickness word lines with reduced length metal nitride diffusion barriers and methods for forming the same

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film. The memory film includes a contoured blocking dielectric layer including sac-shaped lateral protrusions located at levels of the electrically conductive layers, a tunneling dielectric layer in contact with the vertical semiconductor channel, and a vertical stack of charge storage material portions located within volumes enclosed by the sac-shaped lateral protrusions.

A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask.

A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

Methods and apparatuses for forming semiconductor devices containing tungsten layers using a tungsten growth suppressant

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Fremont, CA, United States of America

Rahul Sharangpani