Altera Corporation

Rahul Saini

Andy Louie Lee

Bruce B Pedersen

David Lewis

Gregg William Baeckler

Sinan Kaptanoglu

James G Schleicher

Henry Kim

Richard Yuan

Mike Hutton

Michael David Hutton

David Edward Jefferson

Ninh D Ngo

Adam J Wright

Paul J Tracy

Changsong Zhang

Anthony Pang

Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Omnibus logic element

Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Omnibus logic element for packing or fracturing

Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

A method and system to reduce power usage of memory within a programmable logic device (PLD) is disclosed. In one embodiment, a memory block is formed from a plurality of memory sub-blocks. A data management circuit is used to programmably couple bitlines and/or wordlines to a selected number of memory sub-blocks necessary for respective read/write operations. During a respective read operation, the data management circuit uses row and/or column addresses to determine which memory bitlines and/or wordlines, and memory sub-blocks are essential in the read operation, leaving other non-essential bitlines and/or wordlines, and memory sub-blocks idle, thereby conserving power usage of the entire memory block. In one embodiment, a during respective read operation, a series of programmable pass-gates are used to selectively de-couple bitlines and/or wordlines, and memory sub-blocks that are not essential to the read operation.

Reduced power usage in a memory for a programmable logic device

A programmable device can configure memory access parameters to optimize the performance of one or more of its memory units. A memory unit includes one or more programmable delay units connected with clock, control and/or data signals. The configuration data of the programmable device specifies delay values for each programmable delay unit. A programmable delay unit includes at least two signal paths having different timing characteristics. A switching circuit controlled by configuration data is used to select one of the signal paths as the output of the programmable delay unit. Programmable delay units can be connected in series or in parallel to increase the number of possible delays and/or to specify timing parameters of portions of the memory unit in absolute or relative terms. Programmable delay units can be used to vary the timing characteristics of the memory unit and to control the voltage split used to read data.

Programmable memory access parameters

An embodiment of the present invention provides a programmable logic device ('PLD') including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.

Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method

Disclosed is an LE that can provide a number of advantageous feature. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Omnibus logic element including look up table based logic elements

A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.

Method and apparatus for testing interconnect bridging faults in an FPGA

Additional circuitry is provided over a shared-LUT logic circuit to allow functions of different input characteristics to share a logic element which was conventionally illegal. More restrictive circuitry may be provided over a shared-LUT logic circuit to allow functions with particular input characteristics.

Growing community of inventors

Union City, CA, United States of America

Rahul Saini