International Business Machines Corporation

Rahul Rao

Arun Joseph

Pradeep Kumar Nalla

Suriya T Skariah

Arya Madhusoodanan

Anand Haridass

Daniel Lewis

Mithula Madiraju

Manoj Dusanapudi

Prasanna Jayaraman

Venkatesh Sainath

Ashutosh Misra

Vaidyanathan Srinivasan

Preetham M Lobo

Raj Kumar Gajavelly

Michael Alexander Bowen

George Antony

Spandana V Rachamalla

Naiju K Abdul

Shashidhar Reddy

Amanda Christine Venton

Jayaprakash Udhayakumar

Adarsh Subramanya

Fabrication of an electronic circuit is facilitated by providing a computer tool to enhance design of the electronic circuit to meet a design criteria. The computer tool facilitates obtaining one or more hybrid logical entities, where a hybrid logical entity includes a pull-up circuit and a pull-down circuit formed of transistors with different transistor types for pull-up versus pull-down, and different voltage thresholds for pull-up versus pull-down. Further, the facilitating includes incorporating the hybrid logical entity into the electronic circuit design to produce a revised electronic circuit design. The method further includes initiating manufacture of the electronic circuit pursuant, at least in part, to the revised electronic circuit design.

Electronic circuits including hybrid voltage threshold logical entities

Methods and systems for circuit design are described. A tool may detect a timing violation on a signal path connected to a local clock buffer in a circuit model. The local clock buffer may be configured to generate a first clock signal having a first pulse width. The tool may determine a first metric associated with a first type of timing violation, and may determine a second metric associated with a second type of timing violation different from the first type of timing violation. The detected timing violation may be one of the first type and second type of timing violations. The tool may, based on the first metric and the second metric, determine whether to retain the generation of the first clock signal or to configure the local clock buffer to generate a second clock signal having a second pulse width different from the first pulse width.

Balancing cycle stealing with early mode violations

A computer-implemented method includes receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip. Further, the method includes extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design. Further, the method includes predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block, the predicting performed using a pre-trained machine learning model. Further, the method includes using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

Dynamic abstract generation and synthesis flow with area prediction

Embodiments include predictive antenna diode insertion. Aspects of the invention include obtaining a design of a macro, the design including an internal pin disposed on a first layer of the macro. Aspects of the invention also include determining a length of a wire needed to connect the internal pin to a furthest edge of the macro for each of two layers above the layer the internal pin. Aspects of the invention further include adding, to the design of the macro, an antenna diode to the internal pin based on the determination that an area of the wire needed exceeds a threshold value, wherein the area of the wire is based on the length and a width of the wire.

Predictive antenna diode insertion

A method, a computer system, and a computer program product for scan chain wirelength optimization is provided. Embodiments of the present invention may include obtaining root nodes details from the root nodes. Embodiments of the present invention may include optimizing a connectivity of the root nodes. Embodiments of the present invention may include identifying a best start node and a best end node for each of the root nodes. Embodiments of the present invention may include optimizing child nodes in each of the root nodes. Embodiments of the present invention may include determining that a wirelength of a full tour is shorter or longer than a nearest neighbor. Embodiments of the present invention may include applying or skipping a solution.

Scan chain wirelength optimization using Q-learning based reinforcement learning

Method, apparatus and computer program product for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities comprising extracting design heterogeneity extremities from an RTL design; accounting for the design heterogeneity extremities during macro clock and data signals activity abstraction to generate improved macro activity abstractions; accounting for the design heterogeneity extremities during macro clock and data switching capacitance abstraction to generate improved macro capacitance abstractions; and using improved macro activity abstractions and improved macro capacitance abstractions during hierarchical chip power analysis.

Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities

A method for utilization profiling of thread specific execution units and scheduling software on a multi-core processor is provided. To perform the method, the multi-core processor profiles a workload received for execution by a core of the multi-core processor and logs an execution unit sensitivity to an operating system with respect to the workload. Further, the multi-core processor utilizes the execution unit sensitivity for subsequent workload scheduling to minimize sharing of hardware threads on the same core between workloads with similar execution unit sensitivities.

Utilization profiling and scheduling operations using thread specific execution units usage of a multi-core multi-threaded processor

Examples of techniques for speculation throttling for reliability management are described herein. An aspect includes determining that a power state of a processor is above a speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the speculation throttling threshold, throttling speculation in the processor. Another aspect includes determining that the power state of the processor is above a power proxy threshold, wherein the power proxy threshold is higher than the speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the power proxy threshold, enabling a performance throttle unit of the processor.

Speculation throttling for reliability management

A method, executed by a computer, includes pairing a first core with a second core to form a first core group, wherein each core of the group has a plurality of functional units, transferring instructions received by the first core to the second core for execution via a first inter-core communication bus, and executing the instructions on the second core. A computer system and computer program product corresponding to the above method are also disclosed herein.

Core pairing in multicore systems

A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.

Formal verification driven power modeling and design verification

A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Cross-current power modelling using logic simulation

A method for analyzing power in a circuit includes identifying equivalent elements in a source netlist representing the circuit. Abstract elements are formed combining the equivalent elements of the source netlist. A reduced netlist is formed, substituting the abstract elements in the reduced netlist for the collective equivalent elements in the source netlist. Metrics or properties associated with equivalent elements of the source netlist are combined and associated, in the reduced netlist, with the abstract elements. The reduced netlist can be analyzed with results equivalent to analyzing the source netlist.

On the fly netlist compression in power analysis

A method includes configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, simulating N clock cycles in the circuit to provide performance results for one or more registers in the circuit, wherein N is a selected number of staging levels, selecting one of the one or more registers, comparing the performance results for the selected register to performance results for each of the remaining registers to provide one or more equivalent delay candidate registers, and verifying each of the one or more equivalent delay candidate registers to provide one or more confirmed equivalent delay registers. A corresponding computer program product and computer system are also disclosed.

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Bengaluru, India

Rahul Rao