Intel Corporation

Rahul R Kulkarni

Avinash Sodani

Matthew C Merten

Srikanth T Srinivasan

James Hadley

Justin M Deinlein

Bambang Sutanto

David K Li

A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.

Scheduler implementing dependency matrix having restricted entries

Apparatus, systems and methods for speculative scheduling of uops after allocation are disclosed including an apparatus having logic to schedule a micro-operation (uop) for execution before source data of the uop is ready. The apparatus further includes logic to cancel dispatching of the uop for execution if the source data is invalid. Other implementations are disclosed.

Speculatively scheduling micro-operations after allocation

Growing community of inventors

Portland, OR, United States of America

Rahul R Kulkarni