Intel Corporation

Nvidia Corporation

Rahul P Sathe

Tim Foley

Bimal Poddar

Josef Bo Spjut

Holger Heinrich Gruen

Adam Christopher Marrs

Prasoonkumar Surti

Adam T Lake

Jon N Hasselgren

Marco Salvi

Morgan McGuire

Travis T Schluessler

Tomas G Akenine-Moller

Karthik Vaidyanathan

Gabor Liktor

Saurabh Sharma

Thomas F Raoux

Morgan Samuel McGuire

Oliver A Heim

Paul A Rosen

David Bookout

Abhishek Ventakesh

During the rendering of an image, specific pixels in the image are identified where antialiasing would be helpful. Antialiasing is then performed on these identified pixels, where antialiasing is a technique used to add greater realism to a digital image by smoothing jagged edges. This reduces a cost of performing antialiasing by reducing a number of pixels within an image on which antialiasing is performed.

Adding greater realism to a computer-generated image by smoothing jagged edges within the image in an efficient manner

During the rendering of an image, specific pixels in the image are identified where antialiasing would be helpful. Antialiasing is then performed on these identified pixels, where anti-aliasing is a technique used to add greater realism to a digital image by smoothing jagged edges. This reduces a cost of performing antialiasing by reducing a number of pixels within an image on which antialiasing is performed.

Adding greater realism to a computer-generated image by smoothing jagged edges

One aspect of the disclosure provides a method for rendering an image. The method includes: placing primitives of the image in a screen space; binning the primitives into tiles of the screen space that the primitives touch; and rasterizing the tiles. The aforementioned rasterizing includes shading a subset of the primitives binned to one of the tiles over multiple passes at multiple shading rates, each of the shading rates is based at least on a frequency at which a color being shaded at each pass changes across the screen space, and the subset of the primitives are cached in an on-chip memory of a processor rendering the image between the passes.

Multi-rate shading using replayed screen space tiles

One aspect of the disclosure provides a method for rendering an image. The method includes: placing primitives of the image in a screen space; binning the primitives into tiles of the screen space that the primitives touch; and rasterizing the tiles at one tile of the tiles at a time. The aforementioned rasterizing includes shading a subset of the primitives binned to the one tile at a first shading rate during a first pass and shading the subset of primitives binned to the one tile at a second shading rate during a second pass, the second shading rate is different from the first shading rate, and the aforementioned placing is performed once while the image is rendered.

One embodiment provides for a graphics processing apparatus comprising first logic to rasterize pixel regions associated with multiple interleaved primitives; second logic to shade pixel regions covered by one or more of the multiple interleaved primitives; and third logic to interleave output of the second logic for the multiple interleaved primitives to a single render target, the single render target including output associated with the multiple interleaved primitives.

Architecture for interleaved rasterization and pixel shading for virtual reality and multi-view systems

Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

Optimizing for rendering with clear color

Two primitives may be merged by interpolating vertex attributes at coarse pixel centers. Input attributes are computed as a coverage weighted average of the interpolated vertex attributes. Then coarse pixel shading is performed using the merged primitives.

Merging fragments for coarse pixel shading using a weighted average of the attributes of triangles

In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.

Compiler optimization to reduce the control flow divergence

Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader.

Specialized code paths in GPU processing

A shading rate may be set by analyzing samples within a pixel. Then based on that analysis, a system determines whether to use coarse pixel, pixel or sample shading for a region of pixels. Based on the determined type of shading, the shading rate may be set.

Deferred coarse pixel shading

The power consumption of processor-based devices may be reduced by reducing the consumption of power during graphics processing. In some embodiments, the precision of pixel shading in parts of images where artifacts are less objectionable may be reduced. For example, in areas the user is not directly looking at, precision may be reduced to save power. At the same time, because a person is not focusing on those regions, even if usually perceptible artifacts occur because of the reduced precision, an overall pleasing depiction may be achieved.

Variable precision shading

An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

Techniques and architecture for improved vertex processing

Instead of shading a triangle from the rasterizer as soon as it is known that there is a sample inside the triangle, in accordance with one embodiment, shading is delayed until the triangle beside it, called the neighboring triangle, is received. If there is a neighboring triangle facing the same way, with non-mutually exclusive coverage, meaning that it is not overlapping the same region, then the shader shades only once for the pair of triangles. That is, two separate fragments are merged and treated as one fragment. Specifically, the fragment that is over the pixel center is the one that is used and the other fragment is replaced by merging. The merger happens only over the extent of a pixel and more than one primitive is not shaded at a time. However, multiple merges within a 2&#xd7;2 block of pixels are possible.

Growing community of inventors

Emeryville, CA, United States of America

Rahul P Sathe