Samsung Electronics Co., Ltd.

Rahul Kataria

Abhishek Ghosh

Sajal Mittal

Parvinder Kumar Rana

Aroma Bhat

Hareharan Nagarajan

Rajeela Deshpande

Nikhila C M

Jaskaran Singh Bhatia

Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the Xand Xirrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.

Flip flop circuit

A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.

Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library

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Bengaluru, India

Rahul Kataria