Nxp USA, Inc.

Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Rahul Jain

Chanpreet Singh

Gaurav Gupta

Stephan Matthias Herrmann

Michael Andreas Staudenmaier

Sharath Subramanya Naidu

Bhaskar Dutta

Umesh Chandra Lohani

Manoj Verma

Pranshu Agrawal

Navarshi Dhiman

Nitin Dhamija

According to an embodiment of the present disclosure, a method comprises playing, by the media player, a 360-degree video. The method further comprises recording, by the media player, one or more viewing angles corresponding to a user's viewing of the 360-degree video. Further, the method comprises detecting, by the media player, a video seek event to a seek point of the 360-degree video. The method further comprises playing, by the media player, the 360-degree video from the seek point according to a viewing angle determined based on at least one of (a) a recorded viewing angle and (b) a view mode.

Method and apparatus for playing a 360-degree video

A system-on-chip (SoC) includes first and second processing circuits and a data exchange circuit such that the first processing circuit is configured to process image lines based on corresponding sets of processing attributes. The first processing circuit is further configured to continuously receive and process the image lines one after the other to generate corresponding output data, and the second processing circuit is configured to continuously receive by way of the data exchange circuit, the generated output data for processing the generated output data. The data exchange circuit is thus configured to control data flow between the first processing circuit and the second processing circuit such that the first processing circuit and the second processing circuit parallelly process corresponding data associated with same or different image lines.

System for parallelly processing image lines from multiple image sensors

A system for processing multiple images includes an access serializer, trigger controllers, a first-in-first-out (FIFO) memory, and an image signal processing (ISP) pipeline circuit. The access serializer serializes access requests that are associated with processing of input image lines of the images. The trigger controllers decode corresponding serialized access requests to generate trigger identifiers (IDs), respectively. The FIFO memory receives a corresponding trigger ID from each trigger controller and provides the trigger IDs to the ISP pipeline circuit based on an order of reception of the trigger IDs. The ISP pipeline circuit receives the input image lines associated with the trigger IDs, and based on a corresponding set of configuration parameters associated with the input image lines, processes the input image lines in an order of reception of the trigger IDs, to generate processed image lines, respectively.

System for processing images from multiple image sensors

Embodiments are disclosed that apply adaptive sub-tiles to captured images for distortion correction in vision-based assistance systems and methods. A captured image is processed to generate corrected tiles, and selected numbers of sub-tiles are used to generate each of the corrected tiles depending upon the pixel densities for regions of the captured image. The corrected sub-tiles are combined to form corrected tiles, and corrected tiles are combined for form a corrected image. The corrected image can be used to output control signals to cause actions to be issued to a user of the system such as a driver of a vehicle. For one embodiment, the corrected tiles are generated one at a time, and corrected sub-tiles for each corrected tile are also generated one at a time based upon individual source data blocks determined by a pre-determined sub-tile configuration. Efficient memory use and data transfers are provided.

Adaptive sub-tiles for distortion correction in vision-based assistance systems and methods

A method for reducing dynamic power consumption of an integrated circuit design having flip-flops with an EDA tool that initiates clock gating by gating a clock signal received by the flip-flops. A first set of positive-edge triggered flip-flops and a second set of negative-edge triggered flip-flops, and a first set of OR-type clock gating cells and a second set of AND-type clock gating cells are selected from a technology library. The OR-type clock gating cells are connected to clock input terminals of the first set of positive-edge triggered flip-flops and the AND-type clock gating cells to clock terminals of the second set of negative-edge triggered flip-flops.

System for reducing power consumption of integrated circuit

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Noida, India

Rahul Jain