Synopsys, Inc.

Rahul Gupta

Akhil Thotli

Nitin Bansal

Sriram Kumar Jayanthi

Kailash Kumar

Prateek Singh

Manoj Kumar Reddy Puli

Sri Ram Kumar Jayanthi

A logic circuit includes: a first cascode circuit including: a first transistor, a second transistor, and a third transistor connected in series, the third transistor connected to an output of the first cascode circuit; and a first diode connected in parallel with the third transistor; and a second cascode circuit connected in series with the first cascode circuit, the second cascode circuit including: a fourth transistor, a fifth transistor, and a sixth transistor connected in series, the sixth transistor connected to an output of the second cascode circuit; and a second diode connected in parallel with the sixth transistor; and wherein the output of the first cascode circuit is connected to the output of the second cascode circuit and connects the first cascode circuit in series with the second cascode circuit.

Driver/inverter using lower voltage tolerant devices

A fail tolerant sensor circuit for adjusting an input signal received at an input pad to be provided to an integrated circuit (IC). The circuit includes a sensor input transistor including a first terminal coupled to the input pad, a second terminal coupled to a receiver circuit, and a gate. The circuit further includes a feedback loop that includes a first voltage clamp circuit having an input coupled to the second terminal of the senor input transistor and providing an output, and a first level shifter including an input coupled to the output of the first voltage clamp circuit and providing the feedback output coupled to the gate of the sensor input transistor.

Fail tolerant pad sensor circuit

An electric circuit and a method for filtering glitches are described. The electric circuit includes a filter, an inverter circuit, and a reset circuit. The inverter circuit is electrically coupled to an output of the filter. The reset circuit is electrically coupled to the output of the filter. The reset circuit pulls the output of the filter high when an input signal to the electric circuit and the output of the inverter circuit are both low, pulls the output of the filter low when the input signal to the electric circuit and the output of the inverter circuit are both high, and passes the output of the filter when (i) the input signal to the electric circuit is high and the output of the inverter circuit is low or (ii) the input signal to the electric circuit is low and the output of the inverter circuit is high.

Glitch filter with reset circuit

A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.

Aging-resistant Schmitt receiver circuit

An input buffer circuit includes a tracking circuit that produces a tracking signal and an inverter including a cascade of low voltage switching devices coupled to an output of the tracking circuit. The tracking signal follows a first signal during a first time period and a second signal during a second time period. The tracking circuit is configured to reduce an input high voltage/input low voltage (VIH/VIL) spread.

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Haryana, India

Rahul Gupta